// switch off cpu1,2,3
//write CPU0CLK, 0x1
write CPU1CLK, 0x0
write CPU2CLK, 0x0
write CPU3CLK, 0x0
// cpu0,1,2,3
const irq_tst = 1
const irq_msk = (1 << irq_tst)
// start address IRQ1 - tst
write IA0+irq_tst, 0;
// enable hardw IRQ tst
write IRQHW0, irq_msk
// set high level IRQ tst
write IRQHL0, irq_msk
// overwrite, the CONSTANTS representing the errors encountered
write 0xF000, 0xABCD
expect 127, 0xF000, 0xABCD