Full test of the Data Memory via global bus (only by cpu0) and as RAM.
 The number of the errors, counted by cpu(n) is stored in 0xF001+n location of the DBANK.
 The number of the errors, counted by cpu0 in the test via global bus is stored in 0xF000.

 First 63 errors detected by each cpu while testing the DMEM
 lead to store the corresponding RAM-address in DBANK,
 according to the following map:

 in  F005-F042 - test of DMEM by cpu0
 in  F043-F080 - test of DMEM by cpu1
 in  F081-F0BE - test of DMEM by cpu2
 in  F0BF-F0FC - test of DMEM by cpu3
There is additional option in the program.
If in configuring .tcs file, in I/O space at the address 0x3055 we have 1, the test
will run otherwise - not.
 This option may be usefull in ROBs, if we want this test running in some chips only.
 The code for cpu0 alters the value of 0x3055 after each pretrigger.