Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.3, Apr 2004 Please send any comments to: angelov@kip.uni-heidelberg.de 14:34:40 / 30 Jun 2006 Source code file: SRC/fitred.asm Memory initialisation file: Log file: WRK/cpu0.log Program memory size in words: 4096 Default constants, read from /cad/tools/bin/asm_mimd.inc 1 CPU0 = 2 TRAP3 = 3 CC_SIGNED = 0X14 4 CC_NSIGNED = 0X04 5 CC_ZERO = 0X11 6 CC_NZERO = 0X01 7 CC_OVERFL = 0X13 8 CC_NOVERFL = 0X03 9 CC_NEG = 0X12 10 CC_NNEG = 0X02 11 CC_CARRY = 0X10 12 CC_NCARRY = 0X00 13 CC_BUSY = 0X17 14 CC_NBUSY = 0X07 15 CC_DIVB = 0X15 16 CC_NDIVB = 0X05 17 CC_ERRDIV = 0X16 18 CC_NERRDIV = 0X06 19 CC_UNCOND = 0X0F 20 CC_EQ = 0X11 21 CC_NEQ = 0X01 22 CC_NEG = 0X12 23 CC_POS0 = 0X02 24 CC_LTS = 0X14 25 CC_GES = 0X04 26 CC_LTU = 0X10 27 CC_GEU = 0X00 28 CC_LES = 0X19 29 CC_GTS = 0X09 30 CC_LEU = 0X18 31 CC_GTU = 0X08 32 RR_BYTE = 3 33 RR_WORD = 1 34 RR_DWORD = 0 35 LRA1 = LRA 3, 36 LRA2 = LRA 1, 37 LRA4 = LRA 0, 38 LRA4+ = LRA+ 0, 39 XOR = EOR 40 NOT = COM 41 SHLT = SHL 42 ANDT = AND 43 R0 = PRF[0] 44 R1 = PRF[1] 45 R2 = PRF[2] 46 R3 = PRF[3] 47 R4 = PRF[4] 48 R5 = PRF[5] 49 R6 = PRF[6] 50 R7 = PRF[7] 51 R8 = PRF[8] 52 R9 = PRF[9] 53 R10 = PRF[10] 54 R11 = PRF[11] 55 R12 = PRF[12] 56 R13 = PRF[13] 57 R14 = PRF[14] 58 R15 = PRF[15] 59 G0 = GRF[0] 60 G1 = GRF[1] 61 G2 = GRF[2] 62 G3 = GRF[3] 63 G4 = GRF[4] 64 G5 = GRF[5] 65 G6 = GRF[6] 66 G7 = GRF[7] 67 G8 = GRF[8] 68 G9 = GRF[9] 69 G10 = GRF[10] 70 G11 = GRF[11] 71 G12 = GRF[12] 72 G13 = GRF[13] 73 G14 = GRF[14] 74 G15 = GRF[15] 75 F0 = FIT[0] 76 F1 = FIT[1] 77 F2 = FIT[2] 78 F3 = FIT[3] 79 F4 = FIT[4] 80 F5 = FIT[5] 81 F6 = FIT[6] 82 F7 = FIT[7] 83 F8 = FIT[8] 84 F9 = FIT[9] 85 F10 = FIT[10] 86 F11 = FIT[11] 87 F12 = FIT[12] 88 F13 = FIT[13] 89 F14 = FIT[14] 90 F15 = FIT[15] 91 C0 = CON[0] 92 C1 = CON[1] 93 C2 = CON[2] 94 C3 = CON[3] 95 C4 = CON[4] 96 C5 = CON[5] 97 C6 = CON[6] 98 C7 = CON[7] 99 C8 = CON[8] 100 C9 = CON[9] 101 C10 = CON[10] 102 C11 = CON[11] 103 C12 = CON[12] 104 C13 = CON[13] 105 C14 = CON[14] 106 C15 = CON[15] 1: ;################################################# 2: ;# 3: ;# Rudimentary Readout Program for TRAP3 chip 4: ;# 5: ;# Marcus Gutfleisch 6: ;# Universität Heidelberg, Kirchhoff-Institut für 7: ;# 8: ;# Heidelberg, 15.10.2004 9: ;# 10: ;################################################# 11: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snm 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- --- 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- --- 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- --- 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- --- 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- --- 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- --- 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- --- 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- --- 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- --- 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- --- 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- --- 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- --- 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- --- 30: #def PASADEL=0x3158; ---- ---- ---- ---- ---- --- 31: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- --- 32: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- --- 33: #def PASADAC=0x315B; ---- ---- ---- ---- ---- --- 34: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaa 35: #def PASASTL=0x315D; ---- ---- ---- ---- ---- --- 36: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- --- 37: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- --- 38: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaa 39: #def ADCINB=0x3051; ---- ---- ---- ---- ---- --- 40: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- --- 41: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssb 42: #def ADCTST=0x3054; ---- ---- ---- ---- ---- --- 43: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- --- 44: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- --- 45: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- --- 46: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- --- 47: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- --- 48: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaa 49: #def SADCEC=0x3166; ---- ---- ---- ---- ---- --- 50: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --A 51: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --A 52: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --A 53: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --A 54: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --A 55: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --A 56: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --A 57: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --A 58: #def SADCMC=0x3170; ---- ---- ---- ---- ---- --- 59: #def SADCOC=0x3171; ---- ---- ---- ---- ---- --- 60: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd ccc 61: #def SADCTC=0x3173; ---- ---- ---- ---- ---- --- 62: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -ea 63: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- --- 64: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- --- 65: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- --- 66: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAA 67: #def TPPT0=0x3000; ---- ---- ---- ---- ---- --- 68: #def TPPAE=0x3004; ---- ---- ---- ---- ---- --- 69: #def TPPGR=0x3003; ---- ---- ---- ---- ---- --- 70: #def FLBY=0x3018; ---- ---- ---- ---- ---- --- 71: #def FLL=0x3100; ---- ---- ---- ---- ---- --- 72: #def FPBY=0x3019; ---- ---- ---- ---- ---- --- 73: #def FPTC=0x3020; ---- ---- ---- ---- ---- --- 74: #def FPNP=0x3021; ---- ---- ---- ---- ---- --- 75: #def FPCL=0x3022; ---- ---- ---- ---- ---- --- 76: #def FPA=0x3060; --dd dddd dddd dddd dddd ddd 77: #def FGBY=0x301A; ---- ---- ---- ---- ---- --- 78: #def FGFn=0x3080; ---- ---- ---- ---- ---- --- 79: #def FGAn=0x30A0; ---- ---- ---- ---- ---- --- 80: #def FGTA=0x3028; ---- ---- ---- ---- ---- ddd 81: #def FGTB=0x3029; ---- ---- ---- ---- ---- ddd 82: #def FGCL=0x302A; ---- ---- ---- ---- ---- --- 83: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd ddd 84: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd ddd 85: #def FTBY=0x301B; ---- ---- ---- ---- ---- --- 86: #def FTAL=0x3030; ---- ---- ---- ---- ---- --d 87: #def FTLL=0x3031; ---- ---- ---- ---- ---- --d 88: #def FTLS=0x3032; ---- ---- ---- ---- ---- --d 89: #def FCBY=0x301C; ---- ---- ---- ---- ---- --- 90: #def FCWn=0x3038; ---- ---- ---- ---- ---- --- 91: #def TPFS=0x3001; ---- ---- ---- ---- ---- --- 92: #def TPFE=0x3002; ---- ---- ---- ---- ---- --- 93: #def TPQS0=0x3005; ---- ---- ---- ---- ---- --- 94: #def TPQE0=0x3006; ---- ---- ---- ---- ---- --- 95: #def TPQS1=0x3007; ---- ---- ---- ---- ---- --- 96: #def TPQE1=0x3008; ---- ---- ---- ---- ---- --- 97: #def TPHT=0x3041; ---- ---- ---- ---- --dd ddd 98: #def TPVBY=0x3043; ---- ---- ---- ---- ---- --- 99: #def TPVT=0x3042; ---- ---- ---- ---- ---- --- 100: #def TPFP=0x3040; ---- ---- ---- ---- ---- --- 101: #def TPL=0x3180; ---- ---- ---- ---- ---- --- 102: #def TPCL=0x3045; ---- ---- ---- ---- ---- --- 103: #def TPCT=0x3044; ---- ---- ---- ---- ---- --- 104: #def TPD=0x3047; ---- ---- ---- ---- ---- --- 105: #def TPH=0x3140; ---- ---- ---- ---- ---- --- 106: #def TPCBY=0x3046; ---- ---- ---- ---- ---- --- 107: #def TPCI0=0x3048; ---- ---- ---- ---- ---- --- 108: #def TPCI1=0x3049; ---- ---- ---- ---- ---- --- 109: #def TPCI2=0x304A; ---- ---- ---- ---- ---- --- 110: #def TPCI3=0x304B; ---- ---- ---- ---- ---- --- 111: #def EBD=0x3009; ---- ---- ---- ---- ---- --- 112: #def EBSF=0x300C; ---- ---- ---- ---- ---- --- 113: #def EBAQA=0x300A; ---- ---- ---- ---- ---- --- 114: #def EBSIM=0x300D; ---- ---- ---- ---- ---- --- 115: #def EBSIA=0x300B; ---- ---- ---- ---- ---- --- 116: #def EBR=0x0800; ---- ---- ---- ---- ---- -pd 117: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pd 118: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pd 119: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pd 120: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pd 121: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pd 122: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pd 123: #def EBW=0x2000; ---- ---- ---- ---- ---- --d 124: #def EBPP=0x300E; ---- ---- ---- ---- ---- --- 125: #def EBPC=0x300F; ---- ---- ---- ---- ---- --- 126: #def EBP0=0x3010; ---- ---- ---- ---- ---- --- 127: #def EBP1=0x3011; ---- ---- ---- ---- ---- --- 128: #def EBP2=0x3012; ---- ---- ---- ---- ---- --- 129: #def EBP3=0x3013; ---- ---- ---- ---- ---- --- 130: #def EBIS=0x3014; ---- ---- ---- ---- ---- --d 131: #def EBIT=0x3015; ---- ---- ---- ---- ---- ddd 132: #def EBIL=0x3016; ---- ---- ---- ---- ---- --- 133: #def EBIN=0x3017; ---- ---- ---- ---- ---- --- 134: #def EBI=0x0980; dddd dddd dddd dddd dddd ddd 135: #def EBI0=0x0980; dddd dddd dddd dddd dddd dd 136: #def EBI1=0x0981; dddd dddd dddd dddd dddd dd 137: #def EBI2=0x0982; dddd dddd dddd dddd dddd dd 138: #def EBI3=0x0983; dddd dddd dddd dddd dddd dd 139: #def EBI4=0x0984; dddd dddd dddd dddd dddd dd 140: #def EBI5=0x0985; dddd dddd dddd dddd dddd dd 141: #def EBI6=0x0986; dddd dddd dddd dddd dddd dd 142: #def EBI7=0x0987; dddd dddd dddd dddd dddd dd 143: #def EBI8=0x0988; dddd dddd dddd dddd dddd dd 144: #def EBI9=0x0989; dddd dddd dddd dddd dddd dd 145: #def EBIA=0x098A; dddd dddd dddd dddd dddd dd 146: #def EBIB=0x098B; dddd dddd dddd dddd dddd dd 147: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- --- 148: #def MEMRW=0xD000; ---- ---- ---- ---- ---- --- 149: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- --- 150: #def DMDELA=0xD002; ---- ---- ---- ---- ---- --- 151: #def DMDELS=0xD003; ---- ---- ---- ---- ---- --- 152: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPN 153: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPN 154: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPN 155: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPN 156: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPN 157: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPN 158: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPN 159: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPN 160: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaa 161: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaa 162: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaa 163: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaa 164: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmm 165: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmm 166: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmm 167: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmm 168: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmm 169: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmm 170: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmm 171: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmm 172: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmm 173: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmm 174: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmm 175: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmm 176: #def NMOD=0x0D40; ---- ---- ---- ---- ---- --- 177: #def NTRO=0x0D43; ---- ---- ---- --ii iddd ccc 178: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt ttt 179: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbb 180: #def NRRO=0x0D44; ---- ---- ---- --ii iddd ccc 181: #def NTP=0x0D46; pppp pppp pppp pppp pppp ppp 182: #def NP0=0x0D48; ---- ---- ---- ---- ---- -pp 183: #def NP1=0x0D49; ---- ---- ---- ---- ---- -pp 184: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -pp 185: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -pp 186: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLL 187: #def NED=0x0D42; ---- ---- ---- ---- orpp ppf 188: #def NDLY=0x0D41; --jj jiii hhhg ggff feee ddd 189: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhh 190: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DS 191: #def NLE=0x00C2; ---- ---- ---- ---- ---- --- 192: #def NFE=0x0DC1; ---- ---- ---- ---- ---- --- 193: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- --- 194: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- --- 195: #def NITM0=0x0A08; ---- ---- ---- ---- --tt ttt 196: #def NITM1=0x0A09; ---- ---- ---- ---- --tt ttt 197: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt ttt 198: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt ttt 199: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd ddd 200: #def SMON=0x0A06; ---- ---- ---- ---- ---- ddd 201: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- ddd 202: #def NODP=0x0000; dddd dddd dddd dddd dddd ddd 203: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- 204: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- 205: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- 206: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- 207: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- 208: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- 209: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- 210: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- *** End of include file /cad/tools/bin/conf_va.inc 13: 14: 15: ;################################################# 16: ;# 17: ;# defines 18: ;# 19: ;################################################# 20: 21: #def endsig_tr = c14 ; end sign 22: #def endsig_rr = c15 ; end sign 23: #def nsamples = c13 ; number o 24: #def ChipPOS = c8 ; Chip Pos 25: #def EventHeader = c9 ; Readout 26: #def EHchip = 28 ; Evenh He 27: #def EventCounter = c12 ; event co 28: #def NI_tmsn_delay = c11 ; programm 29: #def ReadoutFlag = c10 ; bit1: NI 30: ; bit0: SC 31: #def EvtCtrGIOAdr = 0xC0C ; Address 32: 33: #def rstack = r8 ; program 34: #def rio = r14 ; local I/ 35: 36: #ifdef cpu0 37: #def clk_onoff = CPU0SS ; own cloc 38: #def clk_onoff_next = CPU2SS ; for dela 39: #def LSBdata = 0x03 ; LSBs for 40: #def ni_counters = 0xF0E0 ; ni parit 41: #def IRQHW = IRQHW0 ; 42: #def IRQHL = IRQHL0 ; 43: #endif 44: 45: #ifdef cpu1 46: #def clk_onoff = CPU1SS; ; own cloc 47: #def clk_onoff_next = CPU3SS; ; for dela 48: #def LSBdata = 0x02 ; LSBs for 49: #def ni_counters = 0xF0E1 ; ni parit 50: #def IRQHW = IRQHW1 ; 51: #def IRQHL = IRQHL1 ; 52: #endif 53: 54: #ifdef cpu2 55: #def clk_onoff = CPU2SS; ; own cloc 56: #def LSBdata = 0x03 ; LSBs for 57: #def ni_counters = 0xF0E2 ; ni parit 58: #def IRQHW = IRQHW2 ; 59: #def IRQHL = IRQHL2 ; 60: #endif 61: 62: #ifdef cpu3 63: #def clk_onoff = CPU3SS; ; own cloc 64: #def LSBdata = 0x02 ; LSBs for 65: #def ni_counters = 0xF0E3 ; ni parit 66: #def IRQHW = IRQHW3 ; 67: #def IRQHL = IRQHL3 ; 68: #endif 69: 70: 71: ;################################################# 72: ;# 73: ;# 0x000: Infinite Loop at Instruction Memory Rese 74: ;# 75: ;################################################# 76: 77: ORG 0x0; 78: 79: jmpr cc_uncond, 0 0000 : 0000_0100_0000_0000_0000_1111 80: nop 0001 : 0000_0000_0000_0000_0000_0000 81: 82: 83: ;################################################# 84: ;# 85: ;# 0x100: Interrupt Clear Jump Address 86: ;# 87: ;################################################# 88: 89: ORG 0x100; 90: clr: 91: #ifdef cpu0 92: iext b1111_0101_0000_0000_0010_0000; 0100 : 0101_0000_0000_1111_0101_0000 93: mov b1111_0101_0000_0000_0010_0000, r1 0101 : 1100_0110_0000_0100_0000_0001 94: jmpr cc_busy, 0 0102 : 0000_0100_0010_0000_0101_0111 95: sgio r1, SMOFFON ; switch off all NI LVDS 0103 : 0010_1000_0001_1010_0000_0101 96: #endif 97: 98: #ifdef cpu1 99: mov cmd_ext_clr, r0 100: jmpr cc_busy, 0 101: sgio r0, SMCMD ; clear ready (VA) 102: nop 103: #endif 104: 105: #ifdef cpu2 106: nop 107: nop 108: nop 109: nop 110: #endif 111: 112: #ifdef cpu3 113: nop 114: nop 115: nop 116: nop 117: #endif 118: 119: jmpr cc_uncond, 0 0104 : 0000_0100_0010_0000_1000_1111 120: nop 0105 : 0000_0000_0000_0000_0000_0000 121: 122: 123: ;################################################# 124: ;# 125: ;# 0x200: Interrupt Tracklet Processing Jump Addre 126: ;# 127: ;################################################# 128: 129: ORG 0x200; 130: acq: 131: #ifdef cpu0 132: mov b0000_0010_0000, r1 0200 : 1100_0110_0000_0100_0000_0001 133: jmpr cc_busy, 0 0201 : 0000_0100_0100_0000_0011_0111 134: sgio r1, SMOFF ; switch off clk_fil 0202 : 0010_1000_0001_1010_0000_0111 135: #else 136: nop 137: nop 138: nop 139: #endif 140: 141: mov 32, r0 0203 : 1100_0110_0000_0100_0000_0000 142: delay: ; wait a while to 143: sub r0, c1, r0 ; NI are ready for 0204 : 1000_1010_0000_0110_0010_0000 144: jmp cc_nzero, delay ; transition. 0205 : 0000_0100_0000_0000_0000_0001 145: 146: ;#ifdef cpu0 147: ; mov 0xEAD, r0 148: ; #else 149: mov endsig_tr r0 ; load Tracklet En 0206 : 1100_0010_0000_0111_1100_0000 150: ;#endif 151: spio r0 NODP ; Send Tracklet En 0207 : 0010_0000_0000_0000_0000_0000 152: 153: jmpr cc_uncond 0 0208 : 0000_0100_0100_0001_0000_1111 154: nop 0209 : 0000_0000_0000_0000_0000_0000 155: 156: 157: ;################################################# 158: ;# 159: ;# 0x400: Interrupt Raw Data Transmission Jump Add 160: ;# 161: ;################################################# 162: 163: ORG 0x400 164: raw: 165: #ifdef cpu0 166: mov cmd_CPU_done r0 ; CPU0 indicates u 0400 : 1100_0110_1110_0010_0100_0000 167: jmpr cc_busy, 0 0401 : 0000_0100_1000_0000_0011_0111 168: sgio r0 SMCMD; 0402 : 0010_1000_0000_1010_0000_0100 169: jmp cc_uncond, continue ; CPU0 fills FIFO 0403 : 0000_0100_0000_0000_0000_1111 170: #endif 171: 172: #ifdef cpu1 173: nop 174: nop 175: nop 176: jmp cc_uncond, continue ; CPU1 fills FIFO 177: #endif 178: 179: #ifdef cpu2 180: nop 181: nop 182: nop 183: nop 184: #endif 185: 186: #ifdef cpu3 187: nop 188: nop 189: nop 190: nop 191: #endif 192: 193: mov 0, r0 ; switch off own c 0404 : 1100_0110_0000_0000_0000_0000 194: jmpr cc_busy, 0 0405 : 0000_0100_1000_0000_1011_0111 195: sgio r0, clk_onoff; ; CPU2 and CPU3 ar 0406 : 0010_1000_0000_1010_0010_0001 196: jmpr cc_busy, 0 ; They will be sta 0407 : 0000_0100_1000_0000_1111_0111 197: 198: nop 0408 : 0000_0000_0000_0000_0000_0000 199: nop 0409 : 0000_0000_0000_0000_0000_0000 200: nop 040A : 0000_0000_0000_0000_0000_0000 201: nop 040B : 0000_0000_0000_0000_0000_0000 202: 203: continue: 204: 205: 206: 207: ;############################################## 208: ;# Store Start addresses for SCSN transfer via D 209: ;############################################## 210: 211: #ifdef cpu0 ; CPU0 starts at a 212: iext 0xF000 040C : 0101_0000_0000_0000_0000_1111 213: mov 0xF000, rio 040D : 1100_0110_0000_0000_0000_1110 214: #endif 215: 216: #ifdef cpu1 ; CPU1 starts at 217: iext 0xF033 218: mov 0xF033, rio 219: #endif 220: 221: #ifdef cpu2 ; CPU2 starts at 222: iext 0xF065 223: mov 0xF065, rio 224: #endif 225: 226: #ifdef cpu3 ; CPU3 starts at 227: iext 0xF097 228: mov 0xF097, rio ; end C8 229: #endif 230: 231: 232: 233: ;############################################## 234: ;# NI transfer event header (CPU0 only) 235: ;############################################## 236: 237: #ifdef cpu0 238: 239: mov EHchip, r0 ; chip EHchip star 040E : 1100_0110_0000_0011_1000_0000 240: cmp r0, ChipPOS ; and sends event 040F : 1000_1000_0000_0111_0000_0000 241: jmp cc_nzero, no_event_header 0410 : 0000_0100_0000_0000_0000_0001 242: 243: shl 2, EventHeader, r0 ; combine event he 0411 : 1011_0010_0010_0111_0010_0000 244: or r0, c1, r0 ; SOE+"01"+SOE+"01 0412 : 1010_1010_0000_0110_0010_0000 245: shl 15, r0, r1 ; where SOE is the 0413 : 1011_0010_1111_0000_0000_0001 246: shl 1, r1, r1 0414 : 1011_0010_0001_0000_0010_0001 247: or r0, r1, r0 0415 : 1010_1010_0000_0000_0010_0000 248: 249: spio r0 NODP ; NI transfer even 0416 : 0010_0000_0000_0000_0000_0000 250: jmpr cc_busy, 0 ; SCSN transfer ch 0417 : 0000_0100_1000_0010_1111_0111 251: sgio+ r0 0418 : 0011_1100_0000_0000_0000_0000 252: 253: #else 254: 255: nop 256: nop 257: nop 258: nop 259: nop 260: nop 261: nop 262: nop 263: nop 264: nop 265: nop 266: 267: #endif 268: 269: no_event_header: 270: 271: swp rio, rio ; swap DBANK addre 0419 : 0111_1010_0000_0001_1100_1110 272: 273: mov ReadoutFlag, r2 ; load NI&SCSN rea 041A : 1100_0010_0000_0111_0100_0010 274: cmp r2, 0 041B : 1100_1000_0010_0000_0000_0000 275: jmp cc_eq, del_end ; check for transmis 041C : 0000_0100_0000_0000_0001_0001 276: 277: #ifdef cpu0 278: 279: shl 15, ChipPOS, r0 ; combine chip hea 041D : 1011_0010_1111_0111_0000_0000 280: shl 5, r0, r0 ; ChipPOS(8)+Event 041E : 1011_0010_0101_0000_0000_0000 281: or r0, EventCounter, r0 041F : 1010_1010_0000_0111_1000_0000 282: shl 2, r0, r0 0420 : 1011_0010_0010_0000_0000_0000 283: or r0, c3, r0 0421 : 1010_1010_0000_0110_0110_0000 284: shl 2, r0, r0 0422 : 1011_0010_0010_0000_0000_0000 285: 286: spio r0 NODP ; NI transfer chip 0423 : 0010_0000_0000_0000_0000_0000 287: swp rio, rio 0424 : 0111_1010_0000_0001_1100_1110 288: jmpr cc_busy, 0 ; SCSN transfer ch 0425 : 0000_0100_1000_0100_1011_0111 289: sgio+ r0 ; no busy flag che 0426 : 0011_1100_0000_0000_0000_0000 290: swp rio, rio ; till next access 0427 : 0111_1010_0000_0001_1100_1110 291: 292: #else 293: 294: nop 295: nop 296: nop 297: nop 298: nop 299: nop 300: nop 301: nop 302: nop 303: nop 304: nop 305: 306: #endif 307: 308: mov LSBdata, r7 ; pass the two LSB 0428 : 1100_0110_0000_0000_0110_0111 309: 310: iext 0xFFFF0000 ; high word mask f 0429 : 0101_0001_1111_1111_1111_0000 311: mov 0xFFFF0000, r15 042A : 1100_0110_0000_0000_0000_1111 312: 313: mov nsamples, r1 ; initially load n 042B : 1100_0010_0000_0111_1010_0001 314: cmp r1, 0 042C : 1100_1000_0001_0000_0000_0000 315: jmp cc_nzero, run_tmsn ; check for transm 042D : 0000_0100_0000_0000_0000_0001 316: 317: del_end: 318: mov 0x020, r2 ; wait a while to 042E : 1100_0110_0000_0100_0000_0010 319: no_tmsn_del: ; NI are ready for 320: sub r2, c1, r2 ; transition. 042F : 1000_1010_0010_0110_0010_0010 321: jmp cc_nzero, no_tmsn_del 0430 : 0000_0100_0000_0000_0000_0001 322: 323: nop 0431 : 0000_0000_0000_0000_0000_0000 324: jmp cc_uncond, complete_ni_tmsn 0432 : 0000_0100_0000_0000_0000_1111 325: nop 0433 : 0000_0000_0000_0000_0000_0000 326: 327: run_tmsn: 328: 329: 330: ;############################################## 331: ;# NI&SCSN transfer 1st channel 332: ;############################################## 333: 334: mov EBR0, r0 ; address in LIO o 0434 : 1100_0111_0000_0000_0000_0000 335: or r0, rio, rio ; to low word of r 0435 : 1010_1010_0000_0001_1100_1110 336: ; mov nsamples,r1 ; number of sample 337: mvpcr +2, rstack 0436 : 1100_0110_1000_0111_0000_1000 338: jmp cc_uncond, ChTML; 0437 : 0000_0100_0000_0000_0000_1111 339: 340: 341: ;############################################## 342: ;# NI&SCSN transfer 2nd channel 343: ;############################################## 344: 345: and r15, rio, rio 0438 : 1010_0110_1111_0001_1100_1110 346: mov EBR1, r0 ; address in LIO o 0439 : 1100_0111_0000_1000_0000_0000 347: or r0, rio, rio ; to low word of r 043A : 1010_1010_0000_0001_1100_1110 348: mov nsamples,r1 ; number of sample 043B : 1100_0010_0000_0111_1010_0001 349: mvpcr +2, rstack 043C : 1100_0110_1000_0111_1100_1000 350: jmp cc_uncond, ChTML; 043D : 0000_0100_0000_0000_0000_1111 351: 352: 353: ;############################################## 354: ;# NI&SCSN transfer 3rd channel 355: ;############################################## 356: 357: and r15, rio, rio 043E : 1010_0110_1111_0001_1100_1110 358: mov EBR2, r0 ; address in LIO o 043F : 1100_0111_0001_0000_0000_0000 359: or r0, rio, rio ; to low word of r 0440 : 1010_1010_0000_0001_1100_1110 360: mov nsamples,r1 ; number of sample 0441 : 1100_0010_0000_0111_1010_0001 361: mvpcr +2, rstack 0442 : 1100_0110_1000_1000_1000_1000 362: jmp cc_uncond, ChTML; 0443 : 0000_0100_0000_0000_0000_1111 363: 364: 365: ;############################################## 366: ;# NI&SCSN transfer 4th channel 367: ;############################################## 368: 369: and r15, rio, rio 0444 : 1010_0110_1111_0001_1100_1110 370: mov EBR3, r0 ; address in LIO o 0445 : 1100_0111_0001_1000_0000_0000 371: or r0, rio, rio ; to low word of r 0446 : 1010_1010_0000_0001_1100_1110 372: mov nsamples,r1 ; number of sample 0447 : 1100_0010_0000_0111_1010_0001 373: mvpcr +2, rstack 0448 : 1100_0110_1000_1001_0100_1000 374: jmp cc_uncond, ChTML; 0449 : 0000_0100_0000_0000_0000_1111 375: 376: 377: ;############################################## 378: ;# NI&SCSN transfer 5th channel 379: ;############################################## 380: 381: and r15, rio, rio 044A : 1010_0110_1111_0001_1100_1110 382: mov EBR4, r0 ; address in LIO o 044B : 1100_0111_0010_0000_0000_0000 383: or r0, rio, rio ; to low word of r 044C : 1010_1010_0000_0001_1100_1110 384: mov nsamples,r1 ; number of sample 044D : 1100_0010_0000_0111_1010_0001 385: mvpcr +2, rstack 044E : 1100_0110_1000_1010_0000_1000 386: jmp cc_uncond, ChTML; 044F : 0000_0100_0000_0000_0000_1111 387: 388: 389: ;############################################## 390: ;# NI&SCSN transfer 6th channel (CPU3 only) 391: ;############################################## 392: 393: #ifdef cpu3 394: and r15, rio, rio 395: mov EBR5, r0 ; address in LIO o 396: or r0, rio, rio ; to low word of r 397: mov nsamples,r1 ; number of sample 398: mvpcr +2, rstack 399: jmp cc_uncond, ChTML; 400: #else 401: nop 0450 : 0000_0000_0000_0000_0000_0000 402: nop 0451 : 0000_0000_0000_0000_0000_0000 403: nop 0452 : 0000_0000_0000_0000_0000_0000 404: nop 0453 : 0000_0000_0000_0000_0000_0000 405: nop 0454 : 0000_0000_0000_0000_0000_0000 406: #endif; 407: 408: 409: ;############################################## 410: ;# Slow down NI transmission if NI_tmsn_delay != 411: ;############################################## 412: 413: complete_ni_tmsn: 414: nop 0455 : 0000_0000_0000_0000_0000_0000 415: 416: #ifdef cpu3 417: 418: mov NI_tmsn_delay, r1 ; mov does 419: andt r1, r1 420: jmp cc_zero, end_ni_tmsn 421: cli 422: mov 0x015, r1 423: mov 0x415, r0 424: sgio r0, IRQHW 425: jmpr cc_busy, 0 426: sgio r0, IRQHL 427: jmpr cc_busy, 0 428: jmp cc_uncond, coff 429: #else 430: nop 0456 : 0000_0000_0000_0000_0000_0000 431: nop 0457 : 0000_0000_0000_0000_0000_0000 432: nop 0458 : 0000_0000_0000_0000_0000_0000 433: nop 0459 : 0000_0000_0000_0000_0000_0000 434: nop 045A : 0000_0000_0000_0000_0000_0000 435: nop 045B : 0000_0000_0000_0000_0000_0000 436: nop 045C : 0000_0000_0000_0000_0000_0000 437: nop 045D : 0000_0000_0000_0000_0000_0000 438: nop 045E : 0000_0000_0000_0000_0000_0000 439: nop 045F : 0000_0000_0000_0000_0000_0000 440: nop 0460 : 0000_0000_0000_0000_0000_0000 441: #endif 442: 443: 444: 445: 446: 447: ;############################################## 448: ;# CPU0, CPU1: start CPU2 and CPU3 for delayed t 449: ;############################################## 450: 451: end_ni_tmsn: 452: mov 1, r1 0461 : 1100_0110_0000_0000_0010_0001 453: 454: #ifdef cpu0 455: jmpr cc_busy, 0 0462 : 0000_0100_1000_1100_0101_0111 456: sgio r1 clk_onoff_next 0463 : 0010_1000_0001_1010_0010_0101 457: #endif 458: 459: #ifdef cpu1 460: jmpr cc_busy, 0 461: sgio r1 clk_onoff_next 462: #endif 463: 464: #ifdef cpu2 465: nop 466: nop 467: #endif 468: 469: #ifdef cpu3 470: nop 471: nop 472: #endif 473: 474: 475: ;############################################## 476: ;# CPU3: Increment Event Counter 477: ;############################################## 478: 479: #ifdef cpu3 480: 481: mov EventCounter, r0 482: add r0, c1, r0 483: iext 0x1FFFFF 484: mov 0x1FFFFF, r1 485: and r1, r0, r0 486: jmp cc_nzero, EvtCtrOK 487: mov 10, r0 488: EvtCtrOK: 489: jmpr cc_busy, 0 490: sgio r0 EvtCtrGIOAdr 491: 492: #else 493: 494: nop 0464 : 0000_0000_0000_0000_0000_0000 495: nop 0465 : 0000_0000_0000_0000_0000_0000 496: nop 0466 : 0000_0000_0000_0000_0000_0000 497: nop 0467 : 0000_0000_0000_0000_0000_0000 498: nop 0468 : 0000_0000_0000_0000_0000_0000 499: nop 0469 : 0000_0000_0000_0000_0000_0000 500: nop 046A : 0000_0000_0000_0000_0000_0000 501: nop 046B : 0000_0000_0000_0000_0000_0000 502: nop 046C : 0000_0000_0000_0000_0000_0000 503: 504: #endif 505: 506: ;############################################## 507: ;# NI&SCSN transfer end marker 508: ;############################################## 509: 510: mov endsig_rr r0 046D : 1100_0010_0000_0111_1110_0000 511: spio r0 NODP 046E : 0010_0000_0000_0000_0000_0000 512: swp rio, rio 046F : 0111_1010_0000_0001_1100_1110 513: jmpr cc_busy, 0 0470 : 0000_0100_1000_1110_0001_0111 514: ; sgio+ r0 515: swp rio, rio 0471 : 0111_1010_0000_0001_1100_1110 516: 517: 518: ;############################################## 519: ;# automatically go to clear state if ReadoutFla 520: ;############################################## 521: 522: ; mov ReadoutFlag, r2 ; load NI& 523: ; cmp r2, 0 524: ; jmp cc_nzero, coff ; check for transm 525: ; 526: ; #ifdef cpu3 527: ; mov CMD_CLEAR, r0 ; CPU0 indicates u 528: ; jmpr cc_busy, 0 529: ; sgio r0 SMCMD; 530: ; #else 531: ; nop 532: ; nop 533: ; nop 534: ; #endif 535: 536: 537: 538: ;############################################## 539: ;# switch off own clock after transfer 540: ;############################################## 541: 542: coff: 543: mov 0, r0 0472 : 1100_0110_0000_0000_0000_0000 544: 545: jmpr cc_busy, 0 0473 : 0000_0100_1000_1110_0111_0111 546: sgio r0 clk_onoff 0474 : 0010_1000_0000_1010_0010_0001 547: jmpr cc_busy, 0 0475 : 0000_0100_1000_1110_1011_0111 548: 549: nop 0476 : 0000_0000_0000_0000_0000_0000 550: nop 0477 : 0000_0000_0000_0000_0000_0000 551: nop 0478 : 0000_0000_0000_0000_0000_0000 552: nop 0479 : 0000_0000_0000_0000_0000_0000 553: nop 047A : 0000_0000_0000_0000_0000_0000 554: nop 047B : 0000_0000_0000_0000_0000_0000 555: nop 047C : 0000_0000_0000_0000_0000_0000 556: 557: jmp cc_uncond, coff 047D : 0000_0100_0000_0000_0000_1111 558: nop 047E : 0000_0000_0000_0000_0000_0000 559: 560: 561: 562: ;################################################# 563: ;# 564: ;# NI transmission of one channel 565: ;# 566: ;################################################# 567: ;# 568: ;# Interface: 569: ;# 570: ;# Input: r14 start address of event buf 571: ;# r1 number of time bins to rea 572: ;# r7 OR mask for the 32 bit wor 573: ;# r2 Readout Flags 574: ;# 575: ;# Output: sends data to the NI outpu 576: ;# Modifies: r3, r4, r5, r14, r1 (0) 577: ;# 578: ;################################################# 579: 580: ;################# 581: ;# BEGIN data tran 582: ChTML: ;################# 583: 584: lpio+ r3 ; initial read has 047F : 1110_1110_0000_0000_0000_0011 585: lpio+ r3 ; memory delay (sy 0480 : 1110_1110_0000_0000_0000_0011 586: lpio+ r4 0481 : 1110_1110_0000_0000_0000_0100 587: lpio rio, r5 0482 : 1110_0010_0000_0001_1100_0101 588: 589: shl 10, r5, r5 ; combine three 10 0483 : 1011_0010_1010_0000_1010_0101 590: or r5, r4, r5 ; to one (32=10+10 0484 : 1010_1010_0101_0000_1000_0101 591: shl 10, r5, r5 0485 : 1011_0010_1010_0000_1010_0101 592: or r5, r3, r5 0486 : 1010_1010_0101_0000_0110_0101 593: shl 2, r5, r5 0487 : 1011_0010_0010_0000_1010_0101 594: or r5, r7, r5 ; set the two LSBs 0488 : 1010_1010_0101_0000_1110_0101 595: 596: and r2, c2, r2 ; check NI readout 0489 : 1010_0110_0010_0110_0100_0010 597: jmp cc_zero, scsn_readout 048A : 0000_0100_0000_0000_0001_0001 598: 599: spio r5, NODP ; write to NI 048B : 0010_0000_0101_0000_0000_0000 600: 601: scsn_readout: 602: swp rio, rio ; switch to SCSN s 048C : 0111_1010_0000_0001_1100_1110 603: sgio+ r5 ; write to DBANK f 048D : 0011_1100_0101_0000_0000_0000 604: swp rio, rio ; switch back to e 048E : 0111_1010_0000_0001_1100_1110 605: 606: sub r1, c3, r1 ; decrease number 048F : 1000_1010_0001_0110_0110_0001 607: jmp cc_gtu, ChTML ; loop 0490 : 0000_0100_0000_0000_0000_1000 608: 609: xor r7, c1, r7 0491 : 1010_0010_0111_0110_0010_0111 610: jmp cc_uncond, rstack ; return from subr 0492 : 0000_1000_1000_0000_0000_1111 611: ;################# 612: ;# END data transf 613: ;################# 614: 615: nop 0493 : 0000_0000_0000_0000_0000_0000 616: 617: 618: ;################################################# 619: ;# 620: ;# 0x500: Interrupt NI FIFO empty 621: ;# 622: ;################################################# 623: ; 624: ORG 0x500 625: 626: 627: sgio r1, IRQHL 0500 : 0010_1000_0001_1011_0000_1111 628: jmpr cc_busy, 0 0501 : 0000_0100_1010_0000_0011_0111 629: sgio r1, IRQHW 0502 : 0010_1000_0001_1011_0000_1110 630: jmpr cc_busy, 0 0503 : 0000_0100_1010_0000_0111_0111 631: 632: ; program the delay 633: mov NI_tmsn_delay, r1 0504 : 1100_0010_0000_0111_0110_0001 634: spio r1, 0x200 0505 : 0010_0000_0001_0010_0000_0000 635: mov b1010_0101_1111, r1 ; counter, down, ir 0506 : 1100_0111_0100_1011_1110_0001 636: spio r1, 0x201 0507 : 0010_0000_0001_0010_0000_0001 637: mov b0101_0101, r1 0508 : 1100_0110_0000_1010_1010_0001 638: sgio r1, IRQHL 0509 : 0010_1000_0001_1011_0000_1111 639: jmpr cc_busy, 0 050A : 0000_0100_1010_0001_0101_0111 640: sgio r1, IRQHW 050B : 0010_1000_0001_1011_0000_1110 641: jmpr cc_busy, 0 050C : 0000_0100_1010_0001_1001_0111 642: jmp cc_uncond, coff 050D : 0000_0100_0000_0000_0000_1111 643: 644: 645: ;################################################# 646: ;# 647: ;# 0x600: Interrupt NI FIFO empty 648: ;# 649: ;################################################# 650: ; 651: ORG 0x600 652: 653: ; restore the interrupt mask 654: mov 0x015, r1 0600 : 1100_0110_0000_0010_1010_0001 655: sgio r1, IRQHL 0601 : 0010_1000_0001_1011_0000_1111 656: jmpr cc_busy, 0 0602 : 0000_0100_1100_0000_0101_0111 657: sgio r1, IRQHW 0603 : 0010_1000_0001_1011_0000_1110 658: jmpr cc_busy, 0 0604 : 0000_0100_1100_0000_1001_0111 659: 660: 661: ; send end signature 662: jmp cc_uncond, end_ni_tmsn 0605 : 0000_0100_0000_0000_0000_1111 663: nop 0606 : 0000_0000_0000_0000_0000_0000 Source file read, 0 error(s), 0 warning(s).