Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.3, Apr 2004 Please send any comments to: angelov@kip.uni-heidelberg.de 13:46:05 / 19 Aug 2006 Source code file: SignalProcessing.asm Memory initialisation file: Log file: ../work/cpu0.log Program memory size in words: 4096 Default constants, read from /cad/tools/bin/asm_mimd.inc 1 CPU0 = 2 TRAP3 = 3 CC_SIGNED = 0X14 4 CC_NSIGNED = 0X04 5 CC_ZERO = 0X11 6 CC_NZERO = 0X01 7 CC_OVERFL = 0X13 8 CC_NOVERFL = 0X03 9 CC_NEG = 0X12 10 CC_NNEG = 0X02 11 CC_CARRY = 0X10 12 CC_NCARRY = 0X00 13 CC_BUSY = 0X17 14 CC_NBUSY = 0X07 15 CC_DIVB = 0X15 16 CC_NDIVB = 0X05 17 CC_ERRDIV = 0X16 18 CC_NERRDIV = 0X06 19 CC_UNCOND = 0X0F 20 CC_EQ = 0X11 21 CC_NEQ = 0X01 22 CC_NEG = 0X12 23 CC_POS0 = 0X02 24 CC_LTS = 0X14 25 CC_GES = 0X04 26 CC_LTU = 0X10 27 CC_GEU = 0X00 28 CC_LES = 0X19 29 CC_GTS = 0X09 30 CC_LEU = 0X18 31 CC_GTU = 0X08 32 RR_BYTE = 3 33 RR_WORD = 1 34 RR_DWORD = 0 35 LRA1 = LRA 3, 36 LRA2 = LRA 1, 37 LRA4 = LRA 0, 38 LRA4+ = LRA+ 0, 39 XOR = EOR 40 NOT = COM 41 SHLT = SHL 42 ANDT = AND 43 R0 = PRF[0] 44 R1 = PRF[1] 45 R2 = PRF[2] 46 R3 = PRF[3] 47 R4 = PRF[4] 48 R5 = PRF[5] 49 R6 = PRF[6] 50 R7 = PRF[7] 51 R8 = PRF[8] 52 R9 = PRF[9] 53 R10 = PRF[10] 54 R11 = PRF[11] 55 R12 = PRF[12] 56 R13 = PRF[13] 57 R14 = PRF[14] 58 R15 = PRF[15] 59 G0 = GRF[0] 60 G1 = GRF[1] 61 G2 = GRF[2] 62 G3 = GRF[3] 63 G4 = GRF[4] 64 G5 = GRF[5] 65 G6 = GRF[6] 66 G7 = GRF[7] 67 G8 = GRF[8] 68 G9 = GRF[9] 69 G10 = GRF[10] 70 G11 = GRF[11] 71 G12 = GRF[12] 72 G13 = GRF[13] 73 G14 = GRF[14] 74 G15 = GRF[15] 75 F0 = FIT[0] 76 F1 = FIT[1] 77 F2 = FIT[2] 78 F3 = FIT[3] 79 F4 = FIT[4] 80 F5 = FIT[5] 81 F6 = FIT[6] 82 F7 = FIT[7] 83 F8 = FIT[8] 84 F9 = FIT[9] 85 F10 = FIT[10] 86 F11 = FIT[11] 87 F12 = FIT[12] 88 F13 = FIT[13] 89 F14 = FIT[14] 90 F15 = FIT[15] 91 C0 = CON[0] 92 C1 = CON[1] 93 C2 = CON[2] 94 C3 = CON[3] 95 C4 = CON[4] 96 C5 = CON[5] 97 C6 = CON[6] 98 C7 = CON[7] 99 C8 = CON[8] 100 C9 = CON[9] 101 C10 = CON[10] 102 C11 = CON[11] 103 C12 = CON[12] 104 C13 = CON[13] 105 C14 = CON[14] 106 C15 = CON[15] 1: ;################################################# 2: ;# 3: ;# Test Program for nonlinearity filter. 4: ;# 5: ;# Input data is taken from event buffer and 6: ;# another memory region. 7: ;# 8: ;# Marcus Gutfleisch 9: ;# Ruprecht-Karls-Universität Heidelberg, Kir 10: ;# 11: ;# Heidelberg, 18.03.2005 12: ;# 13: ;################################################# 14: 15: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snm 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- --- 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- --- 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- --- 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- --- 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- --- 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- --- 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- --- 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- --- 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- --- 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- --- 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- --- 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- --- 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- --- 30: #def PASADEL=0x3158; ---- ---- ---- ---- ---- --- 31: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- --- 32: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- --- 33: #def PASADAC=0x315B; ---- ---- ---- ---- ---- --- 34: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaa 35: #def PASASTL=0x315D; ---- ---- ---- ---- ---- --- 36: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- --- 37: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- --- 38: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaa 39: #def ADCINB=0x3051; ---- ---- ---- ---- ---- --- 40: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- --- 41: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssb 42: #def ADCTST=0x3054; ---- ---- ---- ---- ---- --- 43: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- --- 44: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- --- 45: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- --- 46: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- --- 47: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- --- 48: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaa 49: #def SADCEC=0x3166; ---- ---- ---- ---- ---- --- 50: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --A 51: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --A 52: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --A 53: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --A 54: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --A 55: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --A 56: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --A 57: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --A 58: #def SADCMC=0x3170; ---- ---- ---- ---- ---- --- 59: #def SADCOC=0x3171; ---- ---- ---- ---- ---- --- 60: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd ccc 61: #def SADCTC=0x3173; ---- ---- ---- ---- ---- --- 62: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -ea 63: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- --- 64: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- --- 65: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- --- 66: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAA 67: #def TPPT0=0x3000; ---- ---- ---- ---- ---- --- 68: #def TPPAE=0x3004; ---- ---- ---- ---- ---- --- 69: #def TPPGR=0x3003; ---- ---- ---- ---- ---- --- 70: #def FLBY=0x3018; ---- ---- ---- ---- ---- --- 71: #def FLL=0x3100; ---- ---- ---- ---- ---- --- 72: #def FPBY=0x3019; ---- ---- ---- ---- ---- --- 73: #def FPTC=0x3020; ---- ---- ---- ---- ---- --- 74: #def FPNP=0x3021; ---- ---- ---- ---- ---- --- 75: #def FPCL=0x3022; ---- ---- ---- ---- ---- --- 76: #def FPA=0x3060; --dd dddd dddd dddd dddd ddd 77: #def FGBY=0x301A; ---- ---- ---- ---- ---- --- 78: #def FGFn=0x3080; ---- ---- ---- ---- ---- --- 79: #def FGAn=0x30A0; ---- ---- ---- ---- ---- --- 80: #def FGTA=0x3028; ---- ---- ---- ---- ---- ddd 81: #def FGTB=0x3029; ---- ---- ---- ---- ---- ddd 82: #def FGCL=0x302A; ---- ---- ---- ---- ---- --- 83: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd ddd 84: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd ddd 85: #def FTBY=0x301B; ---- ---- ---- ---- ---- --- 86: #def FTAL=0x3030; ---- ---- ---- ---- ---- --d 87: #def FTLL=0x3031; ---- ---- ---- ---- ---- --d 88: #def FTLS=0x3032; ---- ---- ---- ---- ---- --d 89: #def FCBY=0x301C; ---- ---- ---- ---- ---- --- 90: #def FCWn=0x3038; ---- ---- ---- ---- ---- --- 91: #def TPFS=0x3001; ---- ---- ---- ---- ---- --- 92: #def TPFE=0x3002; ---- ---- ---- ---- ---- --- 93: #def TPQS0=0x3005; ---- ---- ---- ---- ---- --- 94: #def TPQE0=0x3006; ---- ---- ---- ---- ---- --- 95: #def TPQS1=0x3007; ---- ---- ---- ---- ---- --- 96: #def TPQE1=0x3008; ---- ---- ---- ---- ---- --- 97: #def TPHT=0x3041; ---- ---- ---- ---- --dd ddd 98: #def TPVBY=0x3043; ---- ---- ---- ---- ---- --- 99: #def TPVT=0x3042; ---- ---- ---- ---- ---- --- 100: #def TPFP=0x3040; ---- ---- ---- ---- ---- --- 101: #def TPL=0x3180; ---- ---- ---- ---- ---- --- 102: #def TPCL=0x3045; ---- ---- ---- ---- ---- --- 103: #def TPCT=0x3044; ---- ---- ---- ---- ---- --- 104: #def TPD=0x3047; ---- ---- ---- ---- ---- --- 105: #def TPH=0x3140; ---- ---- ---- ---- ---- --- 106: #def TPCBY=0x3046; ---- ---- ---- ---- ---- --- 107: #def TPCI0=0x3048; ---- ---- ---- ---- ---- --- 108: #def TPCI1=0x3049; ---- ---- ---- ---- ---- --- 109: #def TPCI2=0x304A; ---- ---- ---- ---- ---- --- 110: #def TPCI3=0x304B; ---- ---- ---- ---- ---- --- 111: #def EBD=0x3009; ---- ---- ---- ---- ---- --- 112: #def EBSF=0x300C; ---- ---- ---- ---- ---- --- 113: #def EBAQA=0x300A; ---- ---- ---- ---- ---- --- 114: #def EBSIM=0x300D; ---- ---- ---- ---- ---- --- 115: #def EBSIA=0x300B; ---- ---- ---- ---- ---- --- 116: #def EBR=0x0800; ---- ---- ---- ---- ---- -pd 117: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pd 118: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pd 119: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pd 120: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pd 121: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pd 122: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pd 123: #def EBW=0x2000; ---- ---- ---- ---- ---- --d 124: #def EBPP=0x300E; ---- ---- ---- ---- ---- --- 125: #def EBPC=0x300F; ---- ---- ---- ---- ---- --- 126: #def EBP0=0x3010; ---- ---- ---- ---- ---- --- 127: #def EBP1=0x3011; ---- ---- ---- ---- ---- --- 128: #def EBP2=0x3012; ---- ---- ---- ---- ---- --- 129: #def EBP3=0x3013; ---- ---- ---- ---- ---- --- 130: #def EBIS=0x3014; ---- ---- ---- ---- ---- --d 131: #def EBIT=0x3015; ---- ---- ---- ---- ---- ddd 132: #def EBIL=0x3016; ---- ---- ---- ---- ---- --- 133: #def EBIN=0x3017; ---- ---- ---- ---- ---- --- 134: #def EBI=0x0980; dddd dddd dddd dddd dddd ddd 135: #def EBI0=0x0980; dddd dddd dddd dddd dddd dd 136: #def EBI1=0x0981; dddd dddd dddd dddd dddd dd 137: #def EBI2=0x0982; dddd dddd dddd dddd dddd dd 138: #def EBI3=0x0983; dddd dddd dddd dddd dddd dd 139: #def EBI4=0x0984; dddd dddd dddd dddd dddd dd 140: #def EBI5=0x0985; dddd dddd dddd dddd dddd dd 141: #def EBI6=0x0986; dddd dddd dddd dddd dddd dd 142: #def EBI7=0x0987; dddd dddd dddd dddd dddd dd 143: #def EBI8=0x0988; dddd dddd dddd dddd dddd dd 144: #def EBI9=0x0989; dddd dddd dddd dddd dddd dd 145: #def EBIA=0x098A; dddd dddd dddd dddd dddd dd 146: #def EBIB=0x098B; dddd dddd dddd dddd dddd dd 147: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- --- 148: #def MEMRW=0xD000; ---- ---- ---- ---- ---- --- 149: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- --- 150: #def DMDELA=0xD002; ---- ---- ---- ---- ---- --- 151: #def DMDELS=0xD003; ---- ---- ---- ---- ---- --- 152: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPN 153: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPN 154: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPN 155: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPN 156: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPN 157: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPN 158: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPN 159: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPN 160: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaa 161: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaa 162: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaa 163: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaa 164: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmm 165: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmm 166: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmm 167: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmm 168: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmm 169: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmm 170: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmm 171: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmm 172: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmm 173: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmm 174: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmm 175: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmm 176: #def NMOD=0x0D40; ---- ---- ---- ---- ---- --- 177: #def NTRO=0x0D43; ---- ---- ---- --ii iddd ccc 178: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt ttt 179: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbb 180: #def NRRO=0x0D44; ---- ---- ---- --ii iddd ccc 181: #def NTP=0x0D46; pppp pppp pppp pppp pppp ppp 182: #def NP0=0x0D48; ---- ---- ---- ---- ---- -pp 183: #def NP1=0x0D49; ---- ---- ---- ---- ---- -pp 184: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -pp 185: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -pp 186: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLL 187: #def NED=0x0D42; ---- ---- ---- ---- orpp ppf 188: #def NDLY=0x0D41; --jj jiii hhhg ggff feee ddd 189: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhh 190: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DS 191: #def NLE=0x00C2; ---- ---- ---- ---- ---- --- 192: #def NFE=0x0DC1; ---- ---- ---- ---- ---- --- 193: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- --- 194: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- --- 195: #def NITM0=0x0A08; ---- ---- ---- ---- --tt ttt 196: #def NITM1=0x0A09; ---- ---- ---- ---- --tt ttt 197: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt ttt 198: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt ttt 199: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd ddd 200: #def SMON=0x0A06; ---- ---- ---- ---- ---- ddd 201: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- ddd 202: #def NODP=0x0000; dddd dddd dddd dddd dddd ddd 203: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- 204: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- 205: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- 206: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- 207: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- 208: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- 209: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- 210: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- *** End of include file /cad/tools/bin/conf_va.inc *** Include file ../../assembler.inc 1: ;#define MCM=1; 2: ;#define WAFER=1; 3: #define ROB=1; *** End of include file ../../assembler.inc 18: 19: 20: 21: ;######################################### 22: ;# 23: ;# defines 24: ;# 25: ;######################################### 26: 27: 28: #def CPU_SYNC = g0 29: 30: 31: #def ERROR_CTR = c8 32: #def OFFSET_CTR = c12 33: #def AL_CTR = c13 34: 35: #def OFFSET_ADR = 0xC04 36: #def AL_ADR = 0xC05 37: 38: #ifdef cpu0 39: #def ERROR_ADR = 0xC00 40: #endif 41: #ifdef cpu1 42: #def ERROR_ADR = 0xC08 43: #endif 44: #ifdef cpu2 45: #def ERROR_ADR = 0xC10 46: #endif 47: #ifdef cpu3 48: #def ERROR_ADR = 0xC18 49: #endif 50: 51: 52: 53: ;######################################### 54: ;# 55: ;# 0x0000: Infinite Loop at Instructi 56: ;# 57: ;######################################### 58: 59: 60: org 0x0000 61: 62: jmpr cc_uncond, 0 0000 : 0000_0100_0000_0000_0000_1111 63: nop 0001 : 0000_0000_0000_0000_0000_0000 64: 65: 66: 67: ;######################################### 68: ;# 69: ;# 0x0010: Interrrupt Clear Jump Addr 70: ;# 71: ;# CPU0: switch off all NI 72: ;# switch off NI cloc 73: ;# switch off preproc 74: ;# switch on filter 75: ;# 76: ;# CPU1: end clear state, a 77: ;# 78: ;# CPU2: get tracklet end s 79: ;# 80: ;# CPU3: get data end signa 81: ;# 82: ;######################################### 83: 84: 85: org 0x0010 86: 87: mov 0, r12 0010 : 1100_0110_0000_0000_0000_1100 88: mov 4, r13 0011 : 1100_0110_0000_0000_1000_1101 89: 90: #ifdef cpu0 91: 92: mov 0, r0 0012 : 1100_0110_0000_0000_0000_0000 93: iext EBD 0013 : 0101_0000_0000_0000_0000_0011 94: mov EBD, r1 0014 : 1100_0110_0000_0001_0010_0001 95: jmpr cc_busy, 0 0015 : 0000_0100_0000_0010_1011_0111 96: sgio r0, r1 0016 : 0010_0100_0000_0000_0010_0000 97: 98: mov 0, CPU_SYNC 0017 : 1100_0110_0000_0000_0001_0000 99: 100: mov CMD_EXT_CLR, r0 0018 : 1100_0110_0110_0010_0100_0000 101: mov CMD_PRETRIGG, r1 0019 : 1100_0110_1010_0010_0100_0001 102: mov 1024, r2 001A : 1100_0110_1000_0000_0000_0010 103: jmpr cc_busy, 0 001B : 0000_0100_0000_0011_0111_0111 104: cmp r2, OFFSET_CTR 001C : 1000_1000_0010_0111_1000_0000 105: jmp cc_leu, end_lp 001D : 0000_0100_0000_0000_0001_1000 106: sgio r0, SMCMD 001E : 0010_1000_0000_1010_0000_0100 107: 108: nop 001F : 0000_0000_0000_0000_0000_0000 109: nop 0020 : 0000_0000_0000_0000_0000_0000 110: sgio r1, SMCMD 0021 : 0010_1000_0001_1010_0000_0100 111: 112: #else 113: 114: #ifdef MCM 115: #ifdef cpu1 116: mov 0, r0 117: iext SEBDOU 118: sgio r0, SEBDOU 119: #else 120: nop 121: nop 122: nop 123: #endif 124: #endif 125: 126: ; nop 127: ; nop 128: ; 129: ; nop 130: ; 131: ; nop 132: ; nop 133: ; nop 134: ; nop 135: ; nop 136: ; nop 137: ; nop 138: ; 139: ; nop 140: ; nop 141: ; nop 142: 143: #endif 144: 145: end_cl: jmpr cc_uncond, 0 0022 : 0000_0100_0000_0100_0100_1111 146: nop 0023 : 0000_0000_0000_0000_0000_0000 147: 148: end_lp: 149: #ifdef MCM 150: mov 5, r0 151: iext SEBDEN 152: sgio r0, SEBDEN 153: #else 154: mov CMD_LP, r0 0024 : 1100_0110_0000_0010_0100_0000 155: sgio r0, SMCMD 0025 : 0010_1000_0000_1010_0000_0100 156: nop 0026 : 0000_0000_0000_0000_0000_0000 157: #endif 158: 159: jmpr cc_uncond, 0 0027 : 0000_0100_0000_0100_1110_1111 160: mov CMD_LP, r0 0028 : 1100_0110_0000_0010_0100_0000 161: sgio r0, SMCMD 0029 : 0010_1000_0000_1010_0000_0100 162: 163: jmpr cc_uncond, 0 002A : 0000_0100_0000_0101_0100_1111 164: nop 002B : 0000_0000_0000_0000_0000_0000 165: 166: 167: 168: ;######################################### 169: ;# 170: ;# 0x0100: Interrrupt Tracklet Proces 171: ;# 172: ;# send delayed tracklet end 173: ;# 174: ;######################################### 175: 176: 177: org 0x0100 178: 179: #ifdef cpu0 180: mov 6, r0 0100 : 1100_0110_0000_0000_1100_0000 181: iext EBD 0101 : 0101_0000_0000_0000_0000_0011 182: mov EBD, r1 0102 : 1100_0110_0000_0001_0010_0001 183: jmpr cc_busy, 0 0103 : 0000_0100_0010_0000_0111_0111 184: sgio r0, r1 0104 : 0010_0100_0000_0000_0010_0000 185: #endif 186: 187: #ifdef cpu1 188: nop 189: nop 190: nop 191: nop 192: nop 193: #endif 194: 195: #ifdef cpu2 196: nop 197: nop 198: nop 199: nop 200: nop 201: #endif 202: 203: #ifdef cpu3 204: mov 1, r0 205: iext EBSIM 206: mov EBSIM, r1 207: jmpr cc_busy, 0 208: sgio r0, r1 209: #endif 210: 211: 212: 213: ;################################# 214: ;# 215: ;# check result 216: ;# 217: ;################################# 218: 219: 220: mov EBR0, r8 ; load cha 0105 : 1100_0111_0000_0000_0000_1000 221: add r8, c1, r8 ; add +1 d 0106 : 1000_0010_1000_0110_0010_1000 222: mov EBR1, r9 0107 : 1100_0111_0000_1000_0000_1001 223: add r9, c1, r9 0108 : 1000_0010_1001_0110_0010_1001 224: mov EBR2, r10 0109 : 1100_0111_0001_0000_0000_1010 225: add r10, c1, r10 010A : 1000_0010_1010_0110_0010_1010 226: mov EBR3, r11 010B : 1100_0111_0001_1000_0000_1011 227: add r11, c1, r11 010C : 1000_0010_1011_0110_0010_1011 228: mov EBR4, r12 010D : 1100_0111_0010_0000_0000_1100 229: add r12, c1, r12 010E : 1000_0010_1100_0110_0010_1100 230: mov EBR5, r13 010F : 1100_0111_0010_1000_0000_1101 231: add r13, c1, r13 0110 : 1000_0010_1101_0110_0010_1101 232: 233: mov 0, r0 ; r0: time 0111 : 1100_0110_0000_0000_0000_0000 234: 235: mov 0, r14 ; r14: slo 0112 : 1100_0110_0000_0000_0000_1110 236: mov 0, r15 ; r15: fas 0113 : 1100_0110_0000_0000_0000_1111 237: 238: mov AL_CTR, r7 ; r7: curr 0114 : 1100_0010_0000_0111_1010_0111 239: 240: mov 0x600, r1 ; r1: curr 0115 : 1100_0110_1100_0000_0000_0001 241: mov 0x200, r2 ; r2: curr 0116 : 1100_0110_0100_0000_0000_0010 242: 243: loopTT: mov 0, r6 ; r6: erro 0117 : 1100_0110_0000_0000_0000_0110 244: 245: ;######################### 246: ;# 247: ;# calculate expected 248: ;# 249: ;######################### 250: 251: mov 31, r3 0118 : 1100_0110_0000_0011_1110_0011 252: add r8, r3, r3 ; source o 0119 : 1000_0010_1000_0000_0110_0011 253: add r0, r3, r3 ; source a 011A : 1000_0010_0000_0000_0110_0011 254: 255: lpio r3, r5 011B : 1110_0010_0000_0000_0110_0101 256: lpio r3, r5 ; input da 011C : 1110_0010_0000_0000_0110_0101 257: 258: shl 2, r5, r3 ; r3: expe 011D : 1011_0010_0010_0000_1010_0011 259: 260: add r14, r15, r4 ; r4: corr 011E : 1000_0010_1110_0001_1110_0100 261: cmp r4, 0xFFF 011F : 1100_1000_0100_1111_1111_1111 262: jmp cc_leu, TTo0 0120 : 0000_0100_0000_0000_0001_1000 263: mov 0xFFF, r4 0121 : 1100_0111_1111_1111_1110_0100 264: 265: TTo0: sub r3, r4, r3 ; r3: expe 0122 : 1000_1010_0011_0000_1000_0011 266: jmp cc_gtu, TTo1 0123 : 0000_0100_0000_0000_0000_1000 267: mov 0, r3 0124 : 1100_0110_0000_0000_0000_0011 268: 269: TTo1: mul32 r7, r3, r4 ; r4: weig 0125 : 1001_0000_0111_0000_0110_1100 270: nop ; r5: stim 0126 : 0000_0000_0000_0000_0000_0000 271: shl -11, r4, r4 0127 : 1011_0011_0101_0000_1000_0100 272: add r4, r14, r5 0128 : 1000_0010_0100_0001_1100_0101 273: cmp r5, 0xFFF 0129 : 1100_1000_0101_1111_1111_1111 274: jmp cc_leu, TTo2 012A : 0000_0100_0000_0000_0001_1000 275: mov 0xFFF, r5 012B : 1100_0111_1111_1111_1110_0101 276: 277: TTo2: mul32 r5, r1, r5 ; r14: upd 012C : 1001_0000_0101_0000_0010_1101 278: nop 012D : 0000_0000_0000_0000_0000_0000 279: shl -11, r5, r14 012E : 1011_0011_0101_0000_1010_1110 280: 281: sub r3, r4, r4 ; r4: weig 012F : 1000_1010_0011_0000_1000_0100 282: add r4, r15, r5 ; r5: stim 0130 : 1000_0010_0100_0001_1110_0101 283: cmp r5, 0xFFF 0131 : 1100_1000_0101_1111_1111_1111 284: jmp cc_leu, TTo3 0132 : 0000_0100_0000_0000_0001_1000 285: mov 0xFFF, r5 0133 : 1100_0111_1111_1111_1110_0101 286: 287: TTo3: mul32 r5, r2, r5 ; r14: upd 0134 : 1001_0000_0101_0000_0100_1101 288: nop 0135 : 0000_0000_0000_0000_0000_0000 289: shl -11, r5, r15 0136 : 1011_0011_0101_0000_1010_1111 290: 291: shl -2, r3, r3 ; -> ( 0137 : 1011_0011_1110_0000_0110_0011 292: 293: ;######################### 294: ;# 295: ;# check value 296: ;# 297: ;######################### 298: 299: TTc0: add r0, r8, r4 ; r4: even 0138 : 1000_0010_0000_0001_0000_0100 300: lpio r4, r5 0139 : 1110_0010_0000_0000_1000_0101 301: lpio r4, r5 ; r5: filt 013A : 1110_0010_0000_0000_1000_0101 302: 303: cmp r3, r5 013B : 1000_1000_0011_0000_1010_0000 304: jmp cc_eq, TTc1 013C : 0000_0100_0000_0000_0001_0001 305: add r6, c1, r6 013D : 1000_0010_0110_0110_0010_0110 306: 307: TTc1: add r0, r9, r4 ; r4: even 013E : 1000_0010_0000_0001_0010_0100 308: lpio r4, r5 013F : 1110_0010_0000_0000_1000_0101 309: lpio r4, r5 ; r5: filt 0140 : 1110_0010_0000_0000_1000_0101 310: 311: cmp r3, r5 0141 : 1000_1000_0011_0000_1010_0000 312: jmp cc_eq, TTc2 0142 : 0000_0100_0000_0000_0001_0001 313: add r6, c1, r6 0143 : 1000_0010_0110_0110_0010_0110 314: 315: TTc2: add r0, r10, r4 ; r4: even 0144 : 1000_0010_0000_0001_0100_0100 316: lpio r4, r5 0145 : 1110_0010_0000_0000_1000_0101 317: lpio r4, r5 ; r5: filt 0146 : 1110_0010_0000_0000_1000_0101 318: 319: cmp r3, r5 0147 : 1000_1000_0011_0000_1010_0000 320: jmp cc_eq, TTc3 0148 : 0000_0100_0000_0000_0001_0001 321: add r6, c1, r6 0149 : 1000_0010_0110_0110_0010_0110 322: 323: TTc3: add r0, r11, r4 ; r4: even 014A : 1000_0010_0000_0001_0110_0100 324: lpio r4, r5 014B : 1110_0010_0000_0000_1000_0101 325: lpio r4, r5 ; r5: filt 014C : 1110_0010_0000_0000_1000_0101 326: 327: cmp r3, r5 014D : 1000_1000_0011_0000_1010_0000 328: jmp cc_eq, TTc4 014E : 0000_0100_0000_0000_0001_0001 329: add r6, c1, r6 014F : 1000_0010_0110_0110_0010_0110 330: 331: TTc4: add r0, r12, r4 ; r4: even 0150 : 1000_0010_0000_0001_1000_0100 332: lpio r4, r5 0151 : 1110_0010_0000_0000_1000_0101 333: lpio r4, r5 ; r5: filt 0152 : 1110_0010_0000_0000_1000_0101 334: 335: cmp r3, r5 0153 : 1000_1000_0011_0000_1010_0000 336: jmp cc_eq, TTc5 0154 : 0000_0100_0000_0000_0001_0001 337: add r6, c1, r6 0155 : 1000_0010_0110_0110_0010_0110 338: 339: #ifdef cpu3 340: TTc5: add r0, r13, r4 ; r4: event 341: lpio r4, r5 342: lpio r4, r5 ; r5: filte 343: 344: cmp r3, r5 345: jmp cc_eq, TTend 346: add r6, c1, r6 347: #else 348: nop 0156 : 0000_0000_0000_0000_0000_0000 349: nop 0157 : 0000_0000_0000_0000_0000_0000 350: nop 0158 : 0000_0000_0000_0000_0000_0000 351: 352: nop 0159 : 0000_0000_0000_0000_0000_0000 353: nop 015A : 0000_0000_0000_0000_0000_0000 354: TTc5: nop 015B : 0000_0000_0000_0000_0000_0000 355: #endif 356: 357: TTend: add r6, ERROR_CTR, r6 015C : 1000_0010_0110_0111_0000_0110 358: jmpr cc_busy, 0 015D : 0000_0100_0010_1011_1011_0111 359: sgio r6, ERROR_ADR 015E : 0010_1000_0110_1100_0000_0000 360: 361: add r0, c1, r0 015F : 1000_0010_0000_0110_0010_0000 362: cmp r0, 31 0160 : 1100_1000_0000_0000_0001_1111 363: jmp cc_ltu, loopTT 0161 : 0000_0100_0000_0000_0001_0000 364: nop 0162 : 0000_0000_0000_0000_0000_0000 365: 366: 367: 368: 369: ;################################# 370: ;# 371: ;# increase counters 372: ;# 373: ;################################# 374: 375: 376: #ifdef cpu3 377: 378: mov 1, r1 379: add r1, AL_CTR, r0 380: cmp r0, 1024 381: jmp cc_ltu, ct_LUT 382: 383: mov 0, r0 384: mov 256, r1 385: add r1, OFFSET_CTR, r1 386: 387: jmpr cc_busy, 0 388: sgio r1, OFFSET_ADR 389: 390: ct_LUT: jmpr cc_busy, 0 391: sgio r0, AL_ADR 392: 393: #else 394: 395: nop 0163 : 0000_0000_0000_0000_0000_0000 396: nop 0164 : 0000_0000_0000_0000_0000_0000 397: nop 0165 : 0000_0000_0000_0000_0000_0000 398: nop 0166 : 0000_0000_0000_0000_0000_0000 399: 400: nop 0167 : 0000_0000_0000_0000_0000_0000 401: nop 0168 : 0000_0000_0000_0000_0000_0000 402: nop 0169 : 0000_0000_0000_0000_0000_0000 403: 404: nop 016A : 0000_0000_0000_0000_0000_0000 405: nop 016B : 0000_0000_0000_0000_0000_0000 406: 407: nop 016C : 0000_0000_0000_0000_0000_0000 408: nop 016D : 0000_0000_0000_0000_0000_0000 409: 410: #endif 411: 412: jmpr cc_busy, 0 016E : 0000_0100_0010_1101_1101_0111 413: 414: 415: 416: ;################################# 417: ;# 418: ;# write next LUT test entrie 419: ;# 420: ;################################# 421: 422: 423: mov AL_CTR, r12 ; r12: nex 016F : 1100_0010_0000_0111_1010_1100 424: 425: iext FTAL 0170 : 0101_0000_0000_0000_0000_0011 426: mov FTAL, r0 0171 : 1100_0110_0000_0110_0000_0000 427: 428: jmpr cc_busy, 0 0172 : 0000_0100_0010_1110_0101_0111 429: sgio r12, r0 0173 : 0010_0100_1100_0000_0000_0000 430: 431: 432: 433: ;################################# 434: ;# 435: ;# write next test pattern in 436: ;# 437: ;################################# 438: 439: 440: #ifdef cpu3 441: 442: mov 0, r0 443: cmp r0, AL_CTR 444: jmp cc_neq, endEB 445: 446: iext EBW 447: mov EBW, r0 448: mov 32, r1 449: add r0, r1, r0 ; r0: even 450: 451: mov EBR5, r6 452: add r6, r1, r6 ; r6: even 453: 454: mov 256, r7 ; data 455: 456: mov 0, r1 ; r1: chan 457: mov 1, r2 ; r2: time 458: 459: loopEB: 460: add r6, r2, r8 ; r8: sing 461: 462: lpio r8, r4 463: lpio r8, r4 ; r4: old 464: add r7, r4, r4 ; r4: new 465: 466: shl 7, r1, r3 467: add r0, r3, r3 468: add r2, r3, r3 469: 470: jmpr cc_busy, 0 ; r3: sing 471: sgio r4, r3 ; r4: data 472: 473: mov 10, r5 474: 475: waitD: sub r5, c1, r5 476: jmp cc_gts, waitD 477: 478: add r1, c1, r1 479: cmp r1, 21 480: jmp cc_ltu, loopEB 481: 482: mov 0, r1 483: add r2, c1, r2 484: cmp r2, 32 485: jmp cc_ltu, loopEB 486: nop 487: endEB: mov 1, CPU_SYNC 488: 489: #else 490: 491: nop 0174 : 0000_0000_0000_0000_0000_0000 492: 493: #endif 494: 495: 496: 497: ;################################# 498: ;# 499: ;# wait for data writing comp 500: ;# 501: ;################################# 502: 503: 504: wsy: mov CPU_SYNC, r0 0175 : 1100_0010_0000_0010_0000_0000 505: cmp r0, 1 0176 : 1100_1000_0000_0000_0000_0001 506: jmp cc_neq, wsy 0177 : 0000_0100_0000_0000_0000_0001 507: 508: 509: ;################################# 510: ;# 511: ;# copy lower indicator words 512: ;# 513: ;################################# 514: 515: 516: #ifdef cpu0 517: mov 0x7B8, r15 0178 : 1100_0110_1111_0111_0000_1111 518: #endif 519: 520: #ifdef cpu1 521: mov 0x7CC, r15 522: #endif 523: 524: #ifdef cpu2 525: mov 0x7E0, r15 526: #endif 527: 528: #ifdef cpu3 529: mov 0x7F4, r15 530: #endif 531: 532: lpio EBI0, r0 0179 : 1110_0111_0011_0000_0000_0000 533: lpio EBI0, r0 017A : 1110_0111_0011_0000_0000_0000 534: sra+ r0 017B : 0011_1000_0000_0000_0000_0000 535: 536: lpio EBI2, r0 017C : 1110_0111_0011_0000_0100_0000 537: lpio EBI2, r0 017D : 1110_0111_0011_0000_0100_0000 538: sra+ r0 017E : 0011_1000_0000_0000_0000_0000 539: 540: lpio EBI4, r0 017F : 1110_0111_0011_0000_1000_0000 541: lpio EBI4, r0 0180 : 1110_0111_0011_0000_1000_0000 542: sra+ r0 0181 : 0011_1000_0000_0000_0000_0000 543: 544: lpio EBI6, r0 0182 : 1110_0111_0011_0000_1100_0000 545: lpio EBI6, r0 0183 : 1110_0111_0011_0000_1100_0000 546: sra+ r0 0184 : 0011_1000_0000_0000_0000_0000 547: 548: lpio EBI8, r0 0185 : 1110_0111_0011_0001_0000_0000 549: lpio EBI8, r0 0186 : 1110_0111_0011_0001_0000_0000 550: sra+ r0 0187 : 0011_1000_0000_0000_0000_0000 551: 552: #ifdef cpu3 553: lpio EBIA, r0 554: lpio EBIA, r0 555: sra+ r0 556: #else 557: nop 0188 : 0000_0000_0000_0000_0000_0000 558: nop 0189 : 0000_0000_0000_0000_0000_0000 559: nop 018A : 0000_0000_0000_0000_0000_0000 560: #endif 561: 562: 563: ;################################# 564: ;# 565: ;# DMEM address to copy event 566: ;# beware: byte address = 4 * 567: ;# 568: ;################################# 569: 570: #ifdef cpu0 571: mov 0x080, r15 018B : 1100_0110_0001_0000_0000_1111 572: #endif 573: 574: #ifdef cpu1 575: mov 0x238, r15 576: #endif 577: 578: #ifdef cpu2 579: mov 0x3F0, r15 580: #endif 581: 582: #ifdef cpu3 583: mov 0x5A8, r15 584: #endif 585: 586: ;################################# 587: ;# 588: ;# channel check bits, absolu 589: ;# 590: ;################################# 591: 592: #ifdef cpu0 593: mov 3, r3 018C : 1100_0110_0000_0000_0110_0011 594: #endif 595: 596: #ifdef cpu1 597: mov 2, r3 598: #endif 599: 600: #ifdef cpu2 601: mov 3, r3 602: #endif 603: 604: #ifdef cpu3 605: mov 2, r3 606: #endif 607: 608: ;################################# 609: ;# 610: ;# copy event buffer data of 611: ;# 612: ;################################# 613: 614: mov EBR0, r14 018D : 1100_0111_0000_0000_0000_1110 615: mov 66, r5 018E : 1100_0110_0000_1000_0100_0101 616: 617: loop0: lpio+ r0 018F : 1110_1110_0000_0000_0000_0000 618: lpio+ r0 0190 : 1110_1110_0000_0000_0000_0000 619: lpio+ r1 0191 : 1110_1110_0000_0000_0000_0001 620: lpio r14, r2 0192 : 1110_0010_0000_0001_1100_0010 621: 622: shl 10, r2, r2 0193 : 1011_0010_1010_0000_0100_0010 623: or r1, r2, r2 0194 : 1010_1010_0001_0000_0100_0010 624: shl 10, r2, r2 0195 : 1011_0010_1010_0000_0100_0010 625: or r0, r2, r2 0196 : 1010_1010_0000_0000_0100_0010 626: shl 2, r2, r2 0197 : 1011_0010_0010_0000_0100_0010 627: or r3, r2, r2 0198 : 1010_1010_0011_0000_0100_0010 628: 629: sra+ r2 0199 : 0011_1000_0010_0000_0000_0000 630: 631: sub r5, c3, r5 019A : 1000_1010_0101_0110_0110_0101 632: jmp cc_gtu, loop0 019B : 0000_0100_0000_0000_0000_1000 633: 634: ;################################# 635: ;# 636: ;# copy event buffer data of 637: ;# 638: ;################################# 639: 640: mov EBR1, r14 019C : 1100_0111_0000_1000_0000_1110 641: mov 66, r5 019D : 1100_0110_0000_1000_0100_0101 642: xor r3, c1, r3 019E : 1010_0010_0011_0110_0010_0011 643: 644: loop1: lpio+ r0 019F : 1110_1110_0000_0000_0000_0000 645: lpio+ r0 01A0 : 1110_1110_0000_0000_0000_0000 646: lpio+ r1 01A1 : 1110_1110_0000_0000_0000_0001 647: lpio r14, r2 01A2 : 1110_0010_0000_0001_1100_0010 648: 649: shl 10, r2, r2 01A3 : 1011_0010_1010_0000_0100_0010 650: or r1, r2, r2 01A4 : 1010_1010_0001_0000_0100_0010 651: shl 10, r2, r2 01A5 : 1011_0010_1010_0000_0100_0010 652: or r0, r2, r2 01A6 : 1010_1010_0000_0000_0100_0010 653: shl 2, r2, r2 01A7 : 1011_0010_0010_0000_0100_0010 654: or r3, r2, r2 01A8 : 1010_1010_0011_0000_0100_0010 655: 656: sra+ r2 01A9 : 0011_1000_0010_0000_0000_0000 657: 658: sub r5, c3, r5 01AA : 1000_1010_0101_0110_0110_0101 659: jmp cc_gtu, loop1 01AB : 0000_0100_0000_0000_0000_1000 660: 661: ;################################# 662: ;# 663: ;# copy event buffer data of 664: ;# 665: ;################################# 666: 667: mov EBR2, r14 01AC : 1100_0111_0001_0000_0000_1110 668: mov 66, r5 01AD : 1100_0110_0000_1000_0100_0101 669: xor r3, c1, r3 01AE : 1010_0010_0011_0110_0010_0011 670: 671: loop2: lpio+ r0 01AF : 1110_1110_0000_0000_0000_0000 672: lpio+ r0 01B0 : 1110_1110_0000_0000_0000_0000 673: lpio+ r1 01B1 : 1110_1110_0000_0000_0000_0001 674: lpio r14, r2 01B2 : 1110_0010_0000_0001_1100_0010 675: 676: shl 10, r2, r2 01B3 : 1011_0010_1010_0000_0100_0010 677: or r1, r2, r2 01B4 : 1010_1010_0001_0000_0100_0010 678: shl 10, r2, r2 01B5 : 1011_0010_1010_0000_0100_0010 679: or r0, r2, r2 01B6 : 1010_1010_0000_0000_0100_0010 680: shl 2, r2, r2 01B7 : 1011_0010_0010_0000_0100_0010 681: or r3, r2, r2 01B8 : 1010_1010_0011_0000_0100_0010 682: 683: sra+ r2 01B9 : 0011_1000_0010_0000_0000_0000 684: 685: sub r5, c3, r5 01BA : 1000_1010_0101_0110_0110_0101 686: jmp cc_gtu, loop2 01BB : 0000_0100_0000_0000_0000_1000 687: 688: ;################################# 689: ;# 690: ;# copy event buffer data of 691: ;# 692: ;################################# 693: 694: mov EBR3, r14 01BC : 1100_0111_0001_1000_0000_1110 695: mov 66, r5 01BD : 1100_0110_0000_1000_0100_0101 696: xor r3, c1, r3 01BE : 1010_0010_0011_0110_0010_0011 697: 698: loop3: lpio+ r0 01BF : 1110_1110_0000_0000_0000_0000 699: lpio+ r0 01C0 : 1110_1110_0000_0000_0000_0000 700: lpio+ r1 01C1 : 1110_1110_0000_0000_0000_0001 701: lpio r14, r2 01C2 : 1110_0010_0000_0001_1100_0010 702: 703: shl 10, r2, r2 01C3 : 1011_0010_1010_0000_0100_0010 704: or r1, r2, r2 01C4 : 1010_1010_0001_0000_0100_0010 705: shl 10, r2, r2 01C5 : 1011_0010_1010_0000_0100_0010 706: or r0, r2, r2 01C6 : 1010_1010_0000_0000_0100_0010 707: shl 2, r2, r2 01C7 : 1011_0010_0010_0000_0100_0010 708: or r3, r2, r2 01C8 : 1010_1010_0011_0000_0100_0010 709: 710: sra+ r2 01C9 : 0011_1000_0010_0000_0000_0000 711: 712: sub r5, c3, r5 01CA : 1000_1010_0101_0110_0110_0101 713: jmp cc_gtu, loop3 01CB : 0000_0100_0000_0000_0000_1000 714: 715: ;################################# 716: ;# 717: ;# copy event buffer data of 718: ;# 719: ;################################# 720: 721: mov EBR4, r14 01CC : 1100_0111_0010_0000_0000_1110 722: mov 66, r5 01CD : 1100_0110_0000_1000_0100_0101 723: xor r3, c1, r3 01CE : 1010_0010_0011_0110_0010_0011 724: 725: loop4: lpio+ r0 01CF : 1110_1110_0000_0000_0000_0000 726: lpio+ r0 01D0 : 1110_1110_0000_0000_0000_0000 727: lpio+ r1 01D1 : 1110_1110_0000_0000_0000_0001 728: lpio r14, r2 01D2 : 1110_0010_0000_0001_1100_0010 729: 730: shl 10, r2, r2 01D3 : 1011_0010_1010_0000_0100_0010 731: or r1, r2, r2 01D4 : 1010_1010_0001_0000_0100_0010 732: shl 10, r2, r2 01D5 : 1011_0010_1010_0000_0100_0010 733: or r0, r2, r2 01D6 : 1010_1010_0000_0000_0100_0010 734: shl 2, r2, r2 01D7 : 1011_0010_0010_0000_0100_0010 735: or r3, r2, r2 01D8 : 1010_1010_0011_0000_0100_0010 736: 737: sra+ r2 01D9 : 0011_1000_0010_0000_0000_0000 738: 739: sub r5, c3, r5 01DA : 1000_1010_0101_0110_0110_0101 740: jmp cc_gtu, loop4 01DB : 0000_0100_0000_0000_0000_1000 741: 742: ;################################# 743: ;# 744: ;# copy event buffer data of 745: ;# 746: ;################################# 747: 748: #ifdef cpu3 749: mov EBR5, r14 750: mov 66, r5 751: xor r3, c1, r3 752: 753: loop5: lpio+ r0 754: lpio+ r0 755: lpio+ r1 756: lpio r14, r2 757: 758: shl 10, r2, r2 759: or r1, r2, r2 760: shl 10, r2, r2 761: or r0, r2, r2 762: shl 2, r2, r2 763: or r3, r2, r2 764: 765: sra+ r2 766: 767: sub r5, c3, r5 768: jmp cc_gtu, loop5 769: #else 770: nop 01DC : 0000_0000_0000_0000_0000_0000 771: nop 01DD : 0000_0000_0000_0000_0000_0000 772: nop 01DE : 0000_0000_0000_0000_0000_0000 773: nop 01DF : 0000_0000_0000_0000_0000_0000 774: nop 01E0 : 0000_0000_0000_0000_0000_0000 775: nop 01E1 : 0000_0000_0000_0000_0000_0000 776: nop 01E2 : 0000_0000_0000_0000_0000_0000 777: nop 01E3 : 0000_0000_0000_0000_0000_0000 778: nop 01E4 : 0000_0000_0000_0000_0000_0000 779: nop 01E5 : 0000_0000_0000_0000_0000_0000 780: nop 01E6 : 0000_0000_0000_0000_0000_0000 781: nop 01E7 : 0000_0000_0000_0000_0000_0000 782: nop 01E8 : 0000_0000_0000_0000_0000_0000 783: nop 01E9 : 0000_0000_0000_0000_0000_0000 784: nop 01EA : 0000_0000_0000_0000_0000_0000 785: nop 01EB : 0000_0000_0000_0000_0000_0000 786: #endif 787: 788: 789: ;################################# 790: ;# 791: ;# end current state, goto cl 792: ;# 793: ;################################# 794: 795: 796: #ifdef cpu3 797: 798: mov 0, r0 799: iext EBSIM 800: mov EBSIM, r1 801: jmpr cc_busy, 0 802: sgio r0, r1 803: 804: mov CMD_CLEAR, r0 805: jmpr cc_busy, 0 806: sgio r0, SMCMD 807: 808: #else 809: 810: nop 01EC : 0000_0000_0000_0000_0000_0000 811: nop 01ED : 0000_0000_0000_0000_0000_0000 812: nop 01EE : 0000_0000_0000_0000_0000_0000 813: nop 01EF : 0000_0000_0000_0000_0000_0000 814: nop 01F0 : 0000_0000_0000_0000_0000_0000 815: 816: nop 01F1 : 0000_0000_0000_0000_0000_0000 817: nop 01F2 : 0000_0000_0000_0000_0000_0000 818: nop 01F3 : 0000_0000_0000_0000_0000_0000 819: 820: #endif 821: 822: 823: 824: ;################################# 825: ;# 826: ;# switch off own clock after 827: ;# 828: ;################################# 829: 830: 831: clkoff: mov 0, r0 01F4 : 1100_0110_0000_0000_0000_0000 832: jmpr cc_busy, 0 01F5 : 0000_0100_0011_1110_1011_0111 833: 834: #ifdef cpu0 835: sgio r0, CPU0SS 01F6 : 0010_1000_0000_1010_0010_0001 836: #endif 837: 838: #ifdef cpu1 839: sgio r0, CPU1SS 840: #endif 841: 842: #ifdef cpu2 843: sgio r0, CPU2SS 844: #endif 845: 846: #ifdef cpu3 847: sgio r0, CPU3SS 848: #endif 849: 850: jmp cc_uncond, clkoff 01F7 : 0000_0100_0000_0000_0000_1111 851: nop 01F8 : 0000_0000_0000_0000_0000_0000 852: 853: 854: 855: ;######################################### 856: ;# 857: ;# 0x0300: Interrrupt Raw Data Readou 858: ;# 859: ;# Nothing to be done here. 860: ;# 861: ;######################################### 862: 863: 864: org 0x300 865: 866: jmp cc_uncond, clkoff 0300 : 0000_0100_0000_0000_0000_1111 867: nop 0301 : 0000_0000_0000_0000_0000_0000 Source file read, 0 error(s), 0 warning(s).