Assembler for MIMD-TRAP2/3 (c) V.Angelov, v3.3, Apr 2004 Please send any comments to: angelov@kip.uni-heidelberg.de 16:39:31 / 03 Aug 2006 Source code file: SignalProcessing.asm Memory initialisation file: Log file: ../work/cpu0.log Program memory size in words: 4096 Default constants, read from /cad/tools/bin/asm_mimd.inc 1 CPU0 = 2 TRAP3 = 3 CC_SIGNED = 0X14 4 CC_NSIGNED = 0X04 5 CC_ZERO = 0X11 6 CC_NZERO = 0X01 7 CC_OVERFL = 0X13 8 CC_NOVERFL = 0X03 9 CC_NEG = 0X12 10 CC_NNEG = 0X02 11 CC_CARRY = 0X10 12 CC_NCARRY = 0X00 13 CC_BUSY = 0X17 14 CC_NBUSY = 0X07 15 CC_DIVB = 0X15 16 CC_NDIVB = 0X05 17 CC_ERRDIV = 0X16 18 CC_NERRDIV = 0X06 19 CC_UNCOND = 0X0F 20 CC_EQ = 0X11 21 CC_NEQ = 0X01 22 CC_NEG = 0X12 23 CC_POS0 = 0X02 24 CC_LTS = 0X14 25 CC_GES = 0X04 26 CC_LTU = 0X10 27 CC_GEU = 0X00 28 CC_LES = 0X19 29 CC_GTS = 0X09 30 CC_LEU = 0X18 31 CC_GTU = 0X08 32 RR_BYTE = 3 33 RR_WORD = 1 34 RR_DWORD = 0 35 LRA1 = LRA 3, 36 LRA2 = LRA 1, 37 LRA4 = LRA 0, 38 LRA4+ = LRA+ 0, 39 XOR = EOR 40 NOT = COM 41 SHLT = SHL 42 ANDT = AND 43 R0 = PRF[0] 44 R1 = PRF[1] 45 R2 = PRF[2] 46 R3 = PRF[3] 47 R4 = PRF[4] 48 R5 = PRF[5] 49 R6 = PRF[6] 50 R7 = PRF[7] 51 R8 = PRF[8] 52 R9 = PRF[9] 53 R10 = PRF[10] 54 R11 = PRF[11] 55 R12 = PRF[12] 56 R13 = PRF[13] 57 R14 = PRF[14] 58 R15 = PRF[15] 59 G0 = GRF[0] 60 G1 = GRF[1] 61 G2 = GRF[2] 62 G3 = GRF[3] 63 G4 = GRF[4] 64 G5 = GRF[5] 65 G6 = GRF[6] 66 G7 = GRF[7] 67 G8 = GRF[8] 68 G9 = GRF[9] 69 G10 = GRF[10] 70 G11 = GRF[11] 71 G12 = GRF[12] 72 G13 = GRF[13] 73 G14 = GRF[14] 74 G15 = GRF[15] 75 F0 = FIT[0] 76 F1 = FIT[1] 77 F2 = FIT[2] 78 F3 = FIT[3] 79 F4 = FIT[4] 80 F5 = FIT[5] 81 F6 = FIT[6] 82 F7 = FIT[7] 83 F8 = FIT[8] 84 F9 = FIT[9] 85 F10 = FIT[10] 86 F11 = FIT[11] 87 F12 = FIT[12] 88 F13 = FIT[13] 89 F14 = FIT[14] 90 F15 = FIT[15] 91 C0 = CON[0] 92 C1 = CON[1] 93 C2 = CON[2] 94 C3 = CON[3] 95 C4 = CON[4] 96 C5 = CON[5] 97 C6 = CON[6] 98 C7 = CON[7] 99 C8 = CON[8] 100 C9 = CON[9] 101 C10 = CON[10] 102 C11 = CON[11] 103 C12 = CON[12] 104 C13 = CON[13] 105 C14 = CON[14] 106 C15 = CON[15] 1: ;################################################# 2: ;# 3: ;# Test Program for nonlinearity filter. 4: ;# 5: ;# Input data is taken from event buffer and 6: ;# another memory region. 7: ;# 8: ;# Marcus Gutfleisch 9: ;# Ruprecht-Karls-Universität Heidelberg, Kir 10: ;# 11: ;# Heidelberg, 18.03.2005 12: ;# 13: ;################################################# 14: 15: *** Include file 1: #def SML0=0x0A00; SSSS RRRR RR-- ---- -itt ttt 2: #def SML1=0x0A01; SSSS RRRR RR-- ---- -itt ttt 3: #def SML2=0x0A02; SSSS RRRR RR-- ---- -itt ttt 4: #def SMMODE=0x0A03; SSSS RRRR RR-- ---- pppp snm 5: #def SMCMD=0x0A04; ---- ---- ---- ---- cccc ccc 6: #def CPU0CLK=0x0A20; ---- ---- ---- ---- ---- --- 7: #def CPU0SS=0x0A21; ---- ---- ---- ---- ---- --- 8: #def CPU1CLK=0x0A22; ---- ---- ---- ---- ---- --- 9: #def CPU1SS=0x0A23; ---- ---- ---- ---- ---- --- 10: #def CPU2CLK=0x0A24; ---- ---- ---- ---- ---- --- 11: #def CPU2SS=0x0A25; ---- ---- ---- ---- ---- --- 12: #def CPU3CLK=0x0A26; ---- ---- ---- ---- ---- --- 13: #def CPU3SS=0x0A27; ---- ---- ---- ---- ---- --- 14: #def NICLK=0x0A28; ---- ---- ---- ---- ---- --- 15: #def NICLKSS=0x0A29; ---- ---- ---- ---- ---- --- 16: #def FILCLK=0x0A2A; ---- ---- ---- ---- ---- --- 17: #def FILCLKSS=0x0A2B; ---- ---- ---- ---- ---- --- 18: #def PRECLK=0x0A2C; ---- ---- ---- ---- ---- --- 19: #def PRECLKSS=0x0A2D; ---- ---- ---- ---- ---- --- 20: #def ADCEN=0x0A2E; ---- ---- ---- ---- ---- --- 21: #def ADCENSS=0x0A2F; ---- ---- ---- ---- ---- --- 22: #def NIODE=0x0A30; ---- ---- ---- ---- ---- --- 23: #def NIODESS=0x0A31; ---- ---- ---- ---- ---- --- 24: #def NIOCE=0x0A32; ---- ---- ---- ---- ---- --- 25: #def NIOCESS=0x0A33; ---- ---- ---- ---- ---- --- 26: #def NIIDE=0x0A34; ---- ---- ---- ---- ---- --- 27: #def NIIDESS=0x0A35; ---- ---- ---- ---- ---- --- 28: #def NIICE=0x0A36; ---- ---- ---- ---- ---- --- 29: #def NIICESS=0x0A37; ---- ---- ---- ---- ---- --- 30: #def PASADEL=0x3158; ---- ---- ---- ---- ---- --- 31: #def PASAPHA=0x3159; ---- ---- ---- ---- ---- --- 32: #def PASAPRA=0x315A; ---- ---- ---- ---- ---- --- 33: #def PASADAC=0x315B; ---- ---- ---- ---- ---- --- 34: #def PASACHM=0x315C; ---- ---- ---- -aaa aaaa aaa 35: #def PASASTL=0x315D; ---- ---- ---- ---- ---- --- 36: #def PASAPR1=0x315E; ---- ---- ---- ---- ---- --- 37: #def PASAPR0=0x315F; ---- ---- ---- ---- ---- --- 38: #def ADCMSK=0x3050; ---- ---- ---a aaaa aaaa aaa 39: #def ADCINB=0x3051; ---- ---- ---- ---- ---- --- 40: #def ADCDAC=0x3052; ---- ---- ---- ---- ---- --- 41: #def ADCPAR=0x3053; ---- ---- ---- --ii iiss ssb 42: #def ADCTST=0x3054; ---- ---- ---- ---- ---- --- 43: #def SADCAZ=0x3055; ---- ---- ---- ---- ---- --- 44: #def SADCTRG=0x3161; ---- ---- ---- ---- ---- --- 45: #def SADCRUN=0x3162; ---- ---- ---- ---- ---- --- 46: #def SADCPWR=0x3163; ---- ---- ---- ---- ---- --- 47: #def SADCSTA=0x3164; ---- ---- ---- ---- ---- --- 48: #def L0TSIM=0x3165; ---- ---- ---- ---- --aa aaa 49: #def SADCEC=0x3166; ---- ---- ---- ---- ---- --- 50: #def SADCC0=0x3168; ---- ---- ---- ---- ---- --A 51: #def SADCC1=0x3169; ---- ---- ---- ---- ---- --A 52: #def SADCC2=0x316A; ---- ---- ---- ---- ---- --A 53: #def SADCC3=0x316B; ---- ---- ---- ---- ---- --A 54: #def SADCC4=0x316C; ---- ---- ---- ---- ---- --A 55: #def SADCC5=0x316D; ---- ---- ---- ---- ---- --A 56: #def SADCC6=0x316E; ---- ---- ---- ---- ---- --A 57: #def SADCC7=0x316F; ---- ---- ---- ---- ---- --A 58: #def SADCMC=0x3170; ---- ---- ---- ---- ---- --- 59: #def SADCOC=0x3171; ---- ---- ---- ---- ---- --- 60: #def SADCGTB=0x3172; hhhh gggg ffff eeee dddd ccc 61: #def SADCTC=0x3173; ---- ---- ---- ---- ---- --- 62: #def ADCCPU=0x0100; ---- ---- ---- ---- ---- -ea 63: #def SEBDEN=0x3178; ---- ---- ---- ---- ---- --- 64: #def SEBDOU=0x3179; ---- ---- ---- ---- ---- --- 65: #def SEBDIN=0x317A; ---- ---- ---- ---- ---- --- 66: #def CHIPID=0x3160; ---- ---- ---- --AA AAAA AAA 67: #def TPPT0=0x3000; ---- ---- ---- ---- ---- --- 68: #def TPPAE=0x3004; ---- ---- ---- ---- ---- --- 69: #def TPPGR=0x3003; ---- ---- ---- ---- ---- --- 70: #def FLBY=0x3018; ---- ---- ---- ---- ---- --- 71: #def FLL=0x3100; ---- ---- ---- ---- ---- --- 72: #def FPBY=0x3019; ---- ---- ---- ---- ---- --- 73: #def FPTC=0x3020; ---- ---- ---- ---- ---- --- 74: #def FPNP=0x3021; ---- ---- ---- ---- ---- --- 75: #def FPCL=0x3022; ---- ---- ---- ---- ---- --- 76: #def FPA=0x3060; --dd dddd dddd dddd dddd ddd 77: #def FGBY=0x301A; ---- ---- ---- ---- ---- --- 78: #def FGFn=0x3080; ---- ---- ---- ---- ---- --- 79: #def FGAn=0x30A0; ---- ---- ---- ---- ---- --- 80: #def FGTA=0x3028; ---- ---- ---- ---- ---- ddd 81: #def FGTB=0x3029; ---- ---- ---- ---- ---- ddd 82: #def FGCL=0x302A; ---- ---- ---- ---- ---- --- 83: #def FGCAn=0x30C0; ---- --dd dddd dddd dddd ddd 84: #def FGCBn=0x30C0; ---- --dd dddd dddd dddd ddd 85: #def FTBY=0x301B; ---- ---- ---- ---- ---- --- 86: #def FTAL=0x3030; ---- ---- ---- ---- ---- --d 87: #def FTLL=0x3031; ---- ---- ---- ---- ---- --d 88: #def FTLS=0x3032; ---- ---- ---- ---- ---- --d 89: #def FCBY=0x301C; ---- ---- ---- ---- ---- --- 90: #def FCWn=0x3038; ---- ---- ---- ---- ---- --- 91: #def TPFS=0x3001; ---- ---- ---- ---- ---- --- 92: #def TPFE=0x3002; ---- ---- ---- ---- ---- --- 93: #def TPQS0=0x3005; ---- ---- ---- ---- ---- --- 94: #def TPQE0=0x3006; ---- ---- ---- ---- ---- --- 95: #def TPQS1=0x3007; ---- ---- ---- ---- ---- --- 96: #def TPQE1=0x3008; ---- ---- ---- ---- ---- --- 97: #def TPHT=0x3041; ---- ---- ---- ---- --dd ddd 98: #def TPVBY=0x3043; ---- ---- ---- ---- ---- --- 99: #def TPVT=0x3042; ---- ---- ---- ---- ---- --- 100: #def TPFP=0x3040; ---- ---- ---- ---- ---- --- 101: #def TPL=0x3180; ---- ---- ---- ---- ---- --- 102: #def TPCL=0x3045; ---- ---- ---- ---- ---- --- 103: #def TPCT=0x3044; ---- ---- ---- ---- ---- --- 104: #def TPD=0x3047; ---- ---- ---- ---- ---- --- 105: #def TPH=0x3140; ---- ---- ---- ---- ---- --- 106: #def TPCBY=0x3046; ---- ---- ---- ---- ---- --- 107: #def TPCI0=0x3048; ---- ---- ---- ---- ---- --- 108: #def TPCI1=0x3049; ---- ---- ---- ---- ---- --- 109: #def TPCI2=0x304A; ---- ---- ---- ---- ---- --- 110: #def TPCI3=0x304B; ---- ---- ---- ---- ---- --- 111: #def EBD=0x3009; ---- ---- ---- ---- ---- --- 112: #def EBSF=0x300C; ---- ---- ---- ---- ---- --- 113: #def EBAQA=0x300A; ---- ---- ---- ---- ---- --- 114: #def EBSIM=0x300D; ---- ---- ---- ---- ---- --- 115: #def EBSIA=0x300B; ---- ---- ---- ---- ---- --- 116: #def EBR=0x0800; ---- ---- ---- ---- ---- -pd 117: #def EBR0=0x0800; ---- ---- ---- ---- ---- -pd 118: #def EBR1=0x0840; ---- ---- ---- ---- ---- -pd 119: #def EBR2=0x0880; ---- ---- ---- ---- ---- -pd 120: #def EBR3=0x08C0; ---- ---- ---- ---- ---- -pd 121: #def EBR4=0x0900; ---- ---- ---- ---- ---- -pd 122: #def EBR5=0x0940; ---- ---- ---- ---- ---- -pd 123: #def EBW=0x2000; ---- ---- ---- ---- ---- --d 124: #def EBPP=0x300E; ---- ---- ---- ---- ---- --- 125: #def EBPC=0x300F; ---- ---- ---- ---- ---- --- 126: #def EBP0=0x3010; ---- ---- ---- ---- ---- --- 127: #def EBP1=0x3011; ---- ---- ---- ---- ---- --- 128: #def EBP2=0x3012; ---- ---- ---- ---- ---- --- 129: #def EBP3=0x3013; ---- ---- ---- ---- ---- --- 130: #def EBIS=0x3014; ---- ---- ---- ---- ---- --d 131: #def EBIT=0x3015; ---- ---- ---- ---- ---- ddd 132: #def EBIL=0x3016; ---- ---- ---- ---- ---- --- 133: #def EBIN=0x3017; ---- ---- ---- ---- ---- --- 134: #def EBI=0x0980; dddd dddd dddd dddd dddd ddd 135: #def EBI0=0x0980; dddd dddd dddd dddd dddd dd 136: #def EBI1=0x0981; dddd dddd dddd dddd dddd dd 137: #def EBI2=0x0982; dddd dddd dddd dddd dddd dd 138: #def EBI3=0x0983; dddd dddd dddd dddd dddd dd 139: #def EBI4=0x0984; dddd dddd dddd dddd dddd dd 140: #def EBI5=0x0985; dddd dddd dddd dddd dddd dd 141: #def EBI6=0x0986; dddd dddd dddd dddd dddd dd 142: #def EBI7=0x0987; dddd dddd dddd dddd dddd dd 143: #def EBI8=0x0988; dddd dddd dddd dddd dddd dd 144: #def EBI9=0x0989; dddd dddd dddd dddd dddd dd 145: #def EBIA=0x098A; dddd dddd dddd dddd dddd dd 146: #def EBIB=0x098B; dddd dddd dddd dddd dddd dd 147: #def ARBTIM=0x0A3F; ---- ---- ---- ---- ---- --- 148: #def MEMRW=0xD000; ---- ---- ---- ---- ---- --- 149: #def MEMCOR=0xD001; ---- ---- ---- ---- ---- --- 150: #def DMDELA=0xD002; ---- ---- ---- ---- ---- --- 151: #def DMDELS=0xD003; ---- ---- ---- ---- ---- --- 152: #def HCNTI0=0xD010; O0CC CCCC CCCC PPPP PPPP PPN 153: #def HCNTI1=0xD011; O0CC CCCC CCCC PPPP PPPP PPN 154: #def HCNTI2=0xD012; O0CC CCCC CCCC PPPP PPPP PPN 155: #def HCNTI3=0xD013; O0CC CCCC CCCC PPPP PPPP PPN 156: #def HCNTD0=0xD014; O0CC CCCC CCCC PPPP PPPP PPN 157: #def HCNTD1=0xD015; O0CC CCCC CCCC PPPP PPPP PPN 158: #def HCNTD2=0xD016; O0CC CCCC CCCC PPPP PPPP PPN 159: #def HCNTD3=0xD017; O0CC CCCC CCCC PPPP PPPP PPN 160: #def IA0=0x0B00; ---- ---- ---- ---- ---- aaa 161: #def IA1=0x0B20; ---- ---- ---- ---- ---- aaa 162: #def IA2=0x0B40; ---- ---- ---- ---- ---- aaa 163: #def IA3=0x0B60; ---- ---- ---- ---- ---- aaa 164: #def IRQSW0=0x0B0D; ---- ---- ---- ---- ---m mmm 165: #def IRQSW1=0x0B2D; ---- ---- ---- ---- ---m mmm 166: #def IRQSW2=0x0B4D; ---- ---- ---- ---- ---m mmm 167: #def IRQSW3=0x0B6D; ---- ---- ---- ---- ---m mmm 168: #def IRQHW0=0x0B0E; ---- ---- ---- ---- ---m mmm 169: #def IRQHW1=0x0B2E; ---- ---- ---- ---- ---m mmm 170: #def IRQHW2=0x0B4E; ---- ---- ---- ---- ---m mmm 171: #def IRQHW3=0x0B6E; ---- ---- ---- ---- ---m mmm 172: #def IRQHL0=0x0B0F; ---- ---- ---- ---- ---m mmm 173: #def IRQHL1=0x0B2F; ---- ---- ---- ---- ---m mmm 174: #def IRQHL2=0x0B4F; ---- ---- ---- ---- ---m mmm 175: #def IRQHL3=0x0B6F; ---- ---- ---- ---- ---m mmm 176: #def NMOD=0x0D40; ---- ---- ---- ---- ---- --- 177: #def NTRO=0x0D43; ---- ---- ---- --ii iddd ccc 178: #def NES=0x0D45; rrrr rrrr rrrr rrrr tttt ttt 179: #def NCUT=0x0D4C; dddd dddd cccc cccc bbbb bbb 180: #def NRRO=0x0D44; ---- ---- ---- --ii iddd ccc 181: #def NTP=0x0D46; pppp pppp pppp pppp pppp ppp 182: #def NP0=0x0D48; ---- ---- ---- ---- ---- -pp 183: #def NP1=0x0D49; ---- ---- ---- ---- ---- -pp 184: #def NP2=0x0D4A; ---- ---- ---- ---- ---- -pp 185: #def NP3=0x0D4B; ---- ---- ---- ---- ---- -pp 186: #def NLP=0x00C1; ---- ---- HHHH HHHH LLLL LLL 187: #def NED=0x0D42; ---- ---- ---- ---- orpp ppf 188: #def NDLY=0x0D41; --jj jiii hhhg ggff feee ddd 189: #def NBND=0x0D47; ---- ---- ---- ---- hhhh hhh 190: #def NLF=0x00C0; ---- ---- ---- ---- ---- -DS 191: #def NLE=0x00C2; ---- ---- ---- ---- ---- --- 192: #def NFE=0x0DC1; ---- ---- ---- ---- ---- --- 193: #def NCTRL=0x0DC0; ---- ---- ---- ---- ---- --- 194: #def NFSM=0x0DC2; ---- ---- ---- ---- ---- --- 195: #def NITM0=0x0A08; ---- ---- ---- ---- --tt ttt 196: #def NITM1=0x0A09; ---- ---- ---- ---- --tt ttt 197: #def NITM2=0x0A0A; ---- ---- ---- ---- --tt ttt 198: #def NIP4D=0x0A0B; ---- ---- ---- ---- --tt ttt 199: #def SMOFFON=0x0A05; ---- ---- dddd dddd dddd ddd 200: #def SMON=0x0A06; ---- ---- ---- ---- ---- ddd 201: #def SMOFF=0x0A07; ---- ---- ---- ---- ---- ddd 202: #def NODP=0x0000; dddd dddd dddd dddd dddd ddd 203: #def CMD_LP=0x0012; ---- ---- ---- ---- ---- 204: #def CMD_ACQ=0x0112; ---- ---- ---- ---- ---- 205: #def CMD_CHK_TST=0x0212; ---- ---- ---- ---- ---- 206: #def CMD_EXT_CLR=0x0312; ---- ---- ---- ---- ---- 207: #def CMD_CLEAR=0x0412; ---- ---- ---- ---- ---- 208: #def CMD_PRETRIGG=0x0512; ---- ---- ---- ---- ---- 209: #def CMD_SELFTP=0x0612; ---- ---- ---- ---- ---- 210: #def CMD_CPU_DONE=0x0712; ---- ---- ---- ---- ---- *** End of include file /cad/tools/bin/conf_va.inc *** Include file ../../assembler.inc 1: ;#define MCM=1; 2: ;#define WAFER=1; 3: #define ROB=1; *** End of include file ../../assembler.inc 18: 19: 20: 21: ;######################################### 22: ;# 23: ;# defines 24: ;# 25: ;######################################### 26: 27: 28: #def CPU_SYNC = g0 29: 30: 31: #def CC_ERROR_CTR = c8 32: #def LV_ERROR_CTR = c9 33: #def OFFSET_CTR = c12 34: #def LS_CTR = c13 35: 36: #def OFFSET_ADR = 0xC04 37: #def AL_ADR = 0xC05 38: 39: #ifdef cpu0 40: #def CC_ERROR_ADR = 0xC00 41: #def LV_ERROR_ADR = 0xC01 42: #endif 43: #ifdef cpu1 44: #def CC_ERROR_ADR = 0xC08 45: #def LV_ERROR_ADR = 0xC09 46: #endif 47: #ifdef cpu2 48: #def CC_ERROR_ADR = 0xC10 49: #def LV_ERROR_ADR = 0xC11 50: #endif 51: #ifdef cpu3 52: #def CC_ERROR_ADR = 0xC18 53: #def LV_ERROR_ADR = 0xC19 54: #endif 55: 56: 57: 58: ;######################################### 59: ;# 60: ;# 0x0000: Infinite Loop at Instructi 61: ;# 62: ;######################################### 63: 64: 65: org 0x0000 66: 67: jmpr cc_uncond, 0 0000 : 0000_0100_0000_0000_0000_1111 68: nop 0001 : 0000_0000_0000_0000_0000_0000 69: 70: 71: 72: ;######################################### 73: ;# 74: ;# 0x0010: Interrrupt Clear Jump Addr 75: ;# 76: ;# CPU0: switch off all NI 77: ;# switch off NI cloc 78: ;# switch off preproc 79: ;# switch on filter 80: ;# 81: ;# CPU1: end clear state, a 82: ;# 83: ;# CPU2: get tracklet end s 84: ;# 85: ;# CPU3: get data end signa 86: ;# 87: ;######################################### 88: 89: 90: org 0x0010 91: 92: mov 0, r12 0010 : 1100_0110_0000_0000_0000_1100 93: mov 4, r13 0011 : 1100_0110_0000_0000_1000_1101 94: 95: #ifdef cpu0 96: 97: mov CMD_EXT_CLR, r0 0012 : 1100_0110_0110_0010_0100_0000 98: mov 1024, r2 0013 : 1100_0110_1000_0000_0000_0010 99: jmpr cc_busy, 0 0014 : 0000_0100_0000_0010_1001_0111 100: cmp r2, OFFSET_CTR 0015 : 1000_1000_0010_0111_1000_0000 101: jmp cc_leu, end_lp 0016 : 0000_0100_0000_0000_0001_1000 102: sgio r0, SMCMD 0017 : 0010_1000_0000_1010_0000_0100 103: 104: #else 105: #ifdef cpu1 106: mov 0, r0 107: iext SEBDOU 108: sgio r0, SEBDOU 109: #else 110: nop 111: nop 112: nop 113: #endif 114: 115: nop 116: nop 117: nop 118: 119: #endif 120: 121: end_cl: jmpr cc_uncond, 0 0018 : 0000_0100_0000_0011_0000_1111 122: nop 0019 : 0000_0000_0000_0000_0000_0000 123: 124: end_lp: 125: #ifdef MCM 126: mov 5, r0 127: iext SEBDEN 128: sgio r0, SEBDEN 129: jmpr cc_busy, 0 130: #endif 131: 132: mov CMD_LP, r0 001A : 1100_0110_0000_0010_0100_0000 133: sgio r0, SMCMD 001B : 0010_1000_0000_1010_0000_0100 134: 135: jmpr cc_uncond, 0 001C : 0000_0100_0000_0011_1000_1111 136: nop 001D : 0000_0000_0000_0000_0000_0000 137: 138: 139: 140: ;######################################### 141: ;# 142: ;# 0x0100: Interrrupt Tracklet Proces 143: ;# 144: ;# send delayed tracklet end 145: ;# 146: ;######################################### 147: 148: 149: org 0x0100 150: 151: #ifdef cpu0 152: mov 6, r0 0100 : 1100_0110_0000_0000_1100_0000 153: iext EBD 0101 : 0101_0000_0000_0000_0000_0011 154: mov EBD, r1 0102 : 1100_0110_0000_0001_0010_0001 155: jmpr cc_busy, 0 0103 : 0000_0100_0010_0000_0111_0111 156: sgio r0, r1 0104 : 0010_0100_0000_0000_0010_0000 157: #endif 158: 159: #ifdef cpu1 160: nop 161: nop 162: nop 163: nop 164: nop 165: #endif 166: 167: #ifdef cpu2 168: nop 169: nop 170: nop 171: nop 172: nop 173: #endif 174: 175: #ifdef cpu3 176: mov 1, r0 177: iext EBSIM 178: mov EBSIM, r1 179: jmpr cc_busy, 0 180: sgio r0, r1 181: #endif 182: 183: 184: 185: ;################################# 186: ;# 187: ;# increase counters (1/3) 188: ;# 189: ;################################# 190: 191: 192: #ifdef cpu3 193: 194: mov 1, r1 195: add r1, LS_CTR, r0 196: jmpr cc_busy, 0 197: sgio r0, AL_ADR 198: 199: #else 200: 201: nop 0105 : 0000_0000_0000_0000_0000_0000 202: nop 0106 : 0000_0000_0000_0000_0000_0000 203: nop 0107 : 0000_0000_0000_0000_0000_0000 204: nop 0108 : 0000_0000_0000_0000_0000_0000 205: 206: #endif 207: 208: jmpr cc_busy, 0 0109 : 0000_0100_0010_0001_0011_0111 209: 210: 211: 212: ;################################# 213: ;# 214: ;# copy lower indicator words 215: ;# 216: ;################################# 217: 218: 219: #ifdef cpu0 220: mov 0x7B8, r15 010A : 1100_0110_1111_0111_0000_1111 221: #endif 222: 223: #ifdef cpu1 224: mov 0x7CC, r15 225: #endif 226: 227: #ifdef cpu2 228: mov 0x7E0, r15 229: #endif 230: 231: #ifdef cpu3 232: mov 0x7F4, r15 233: #endif 234: 235: lpio EBI0, r0 010B : 1110_0111_0011_0000_0000_0000 236: lpio EBI0, r0 010C : 1110_0111_0011_0000_0000_0000 237: sra+ r0 010D : 0011_1000_0000_0000_0000_0000 238: 239: lpio EBI2, r0 010E : 1110_0111_0011_0000_0100_0000 240: lpio EBI2, r0 010F : 1110_0111_0011_0000_0100_0000 241: sra+ r0 0110 : 0011_1000_0000_0000_0000_0000 242: 243: lpio EBI4, r0 0111 : 1110_0111_0011_0000_1000_0000 244: lpio EBI4, r0 0112 : 1110_0111_0011_0000_1000_0000 245: sra+ r0 0113 : 0011_1000_0000_0000_0000_0000 246: 247: lpio EBI6, r0 0114 : 1110_0111_0011_0000_1100_0000 248: lpio EBI6, r0 0115 : 1110_0111_0011_0000_1100_0000 249: sra+ r0 0116 : 0011_1000_0000_0000_0000_0000 250: 251: lpio EBI8, r0 0117 : 1110_0111_0011_0001_0000_0000 252: lpio EBI8, r0 0118 : 1110_0111_0011_0001_0000_0000 253: sra+ r0 0119 : 0011_1000_0000_0000_0000_0000 254: 255: #ifdef cpu3 256: lpio EBIA, r0 257: lpio EBIA, r0 258: sra+ r0 259: #else 260: nop 011A : 0000_0000_0000_0000_0000_0000 261: nop 011B : 0000_0000_0000_0000_0000_0000 262: nop 011C : 0000_0000_0000_0000_0000_0000 263: #endif 264: 265: 266: ;################################# 267: ;# 268: ;# DMEM address to copy event 269: ;# beware: byte address = 4 * 270: ;# 271: ;################################# 272: 273: #ifdef cpu0 274: mov 0x080, r15 011D : 1100_0110_0001_0000_0000_1111 275: #endif 276: 277: #ifdef cpu1 278: mov 0x238, r15 279: #endif 280: 281: #ifdef cpu2 282: mov 0x3F0, r15 283: #endif 284: 285: #ifdef cpu3 286: mov 0x5A8, r15 287: #endif 288: 289: ;################################# 290: ;# 291: ;# channel check bits, absolu 292: ;# 293: ;################################# 294: 295: #ifdef cpu0 296: mov 3, r3 011E : 1100_0110_0000_0000_0110_0011 297: #endif 298: 299: #ifdef cpu1 300: mov 2, r3 301: #endif 302: 303: #ifdef cpu2 304: mov 3, r3 305: #endif 306: 307: #ifdef cpu3 308: mov 2, r3 309: #endif 310: 311: ;################################# 312: ;# 313: ;# copy event buffer data of 314: ;# 315: ;################################# 316: 317: mov EBR0, r14 011F : 1100_0111_0000_0000_0000_1110 318: mov 66, r5 0120 : 1100_0110_0000_1000_0100_0101 319: 320: loop0: lpio+ r0 0121 : 1110_1110_0000_0000_0000_0000 321: lpio+ r0 0122 : 1110_1110_0000_0000_0000_0000 322: lpio+ r1 0123 : 1110_1110_0000_0000_0000_0001 323: lpio r14, r2 0124 : 1110_0010_0000_0001_1100_0010 324: 325: shl 10, r2, r2 0125 : 1011_0010_1010_0000_0100_0010 326: or r1, r2, r2 0126 : 1010_1010_0001_0000_0100_0010 327: shl 10, r2, r2 0127 : 1011_0010_1010_0000_0100_0010 328: or r0, r2, r2 0128 : 1010_1010_0000_0000_0100_0010 329: shl 2, r2, r2 0129 : 1011_0010_0010_0000_0100_0010 330: or r3, r2, r2 012A : 1010_1010_0011_0000_0100_0010 331: 332: sra+ r2 012B : 0011_1000_0010_0000_0000_0000 333: 334: sub r5, c3, r5 012C : 1000_1010_0101_0110_0110_0101 335: jmp cc_gtu, loop0 012D : 0000_0100_0000_0000_0000_1000 336: 337: ;################################# 338: ;# 339: ;# copy event buffer data of 340: ;# 341: ;################################# 342: 343: mov EBR1, r14 012E : 1100_0111_0000_1000_0000_1110 344: mov 66, r5 012F : 1100_0110_0000_1000_0100_0101 345: xor r3, c1, r3 0130 : 1010_0010_0011_0110_0010_0011 346: 347: loop1: lpio+ r0 0131 : 1110_1110_0000_0000_0000_0000 348: lpio+ r0 0132 : 1110_1110_0000_0000_0000_0000 349: lpio+ r1 0133 : 1110_1110_0000_0000_0000_0001 350: lpio r14, r2 0134 : 1110_0010_0000_0001_1100_0010 351: 352: shl 10, r2, r2 0135 : 1011_0010_1010_0000_0100_0010 353: or r1, r2, r2 0136 : 1010_1010_0001_0000_0100_0010 354: shl 10, r2, r2 0137 : 1011_0010_1010_0000_0100_0010 355: or r0, r2, r2 0138 : 1010_1010_0000_0000_0100_0010 356: shl 2, r2, r2 0139 : 1011_0010_0010_0000_0100_0010 357: or r3, r2, r2 013A : 1010_1010_0011_0000_0100_0010 358: 359: sra+ r2 013B : 0011_1000_0010_0000_0000_0000 360: 361: sub r5, c3, r5 013C : 1000_1010_0101_0110_0110_0101 362: jmp cc_gtu, loop1 013D : 0000_0100_0000_0000_0000_1000 363: 364: ;################################# 365: ;# 366: ;# copy event buffer data of 367: ;# 368: ;################################# 369: 370: mov EBR2, r14 013E : 1100_0111_0001_0000_0000_1110 371: mov 66, r5 013F : 1100_0110_0000_1000_0100_0101 372: xor r3, c1, r3 0140 : 1010_0010_0011_0110_0010_0011 373: 374: loop2: lpio+ r0 0141 : 1110_1110_0000_0000_0000_0000 375: lpio+ r0 0142 : 1110_1110_0000_0000_0000_0000 376: lpio+ r1 0143 : 1110_1110_0000_0000_0000_0001 377: lpio r14, r2 0144 : 1110_0010_0000_0001_1100_0010 378: 379: shl 10, r2, r2 0145 : 1011_0010_1010_0000_0100_0010 380: or r1, r2, r2 0146 : 1010_1010_0001_0000_0100_0010 381: shl 10, r2, r2 0147 : 1011_0010_1010_0000_0100_0010 382: or r0, r2, r2 0148 : 1010_1010_0000_0000_0100_0010 383: shl 2, r2, r2 0149 : 1011_0010_0010_0000_0100_0010 384: or r3, r2, r2 014A : 1010_1010_0011_0000_0100_0010 385: 386: sra+ r2 014B : 0011_1000_0010_0000_0000_0000 387: 388: sub r5, c3, r5 014C : 1000_1010_0101_0110_0110_0101 389: jmp cc_gtu, loop2 014D : 0000_0100_0000_0000_0000_1000 390: 391: ;################################# 392: ;# 393: ;# copy event buffer data of 394: ;# 395: ;################################# 396: 397: mov EBR3, r14 014E : 1100_0111_0001_1000_0000_1110 398: mov 66, r5 014F : 1100_0110_0000_1000_0100_0101 399: xor r3, c1, r3 0150 : 1010_0010_0011_0110_0010_0011 400: 401: loop3: lpio+ r0 0151 : 1110_1110_0000_0000_0000_0000 402: lpio+ r0 0152 : 1110_1110_0000_0000_0000_0000 403: lpio+ r1 0153 : 1110_1110_0000_0000_0000_0001 404: lpio r14, r2 0154 : 1110_0010_0000_0001_1100_0010 405: 406: shl 10, r2, r2 0155 : 1011_0010_1010_0000_0100_0010 407: or r1, r2, r2 0156 : 1010_1010_0001_0000_0100_0010 408: shl 10, r2, r2 0157 : 1011_0010_1010_0000_0100_0010 409: or r0, r2, r2 0158 : 1010_1010_0000_0000_0100_0010 410: shl 2, r2, r2 0159 : 1011_0010_0010_0000_0100_0010 411: or r3, r2, r2 015A : 1010_1010_0011_0000_0100_0010 412: 413: sra+ r2 015B : 0011_1000_0010_0000_0000_0000 414: 415: sub r5, c3, r5 015C : 1000_1010_0101_0110_0110_0101 416: jmp cc_gtu, loop3 015D : 0000_0100_0000_0000_0000_1000 417: 418: ;################################# 419: ;# 420: ;# copy event buffer data of 421: ;# 422: ;################################# 423: 424: mov EBR4, r14 015E : 1100_0111_0010_0000_0000_1110 425: mov 66, r5 015F : 1100_0110_0000_1000_0100_0101 426: xor r3, c1, r3 0160 : 1010_0010_0011_0110_0010_0011 427: 428: loop4: lpio+ r0 0161 : 1110_1110_0000_0000_0000_0000 429: lpio+ r0 0162 : 1110_1110_0000_0000_0000_0000 430: lpio+ r1 0163 : 1110_1110_0000_0000_0000_0001 431: lpio r14, r2 0164 : 1110_0010_0000_0001_1100_0010 432: 433: shl 10, r2, r2 0165 : 1011_0010_1010_0000_0100_0010 434: or r1, r2, r2 0166 : 1010_1010_0001_0000_0100_0010 435: shl 10, r2, r2 0167 : 1011_0010_1010_0000_0100_0010 436: or r0, r2, r2 0168 : 1010_1010_0000_0000_0100_0010 437: shl 2, r2, r2 0169 : 1011_0010_0010_0000_0100_0010 438: or r3, r2, r2 016A : 1010_1010_0011_0000_0100_0010 439: 440: sra+ r2 016B : 0011_1000_0010_0000_0000_0000 441: 442: sub r5, c3, r5 016C : 1000_1010_0101_0110_0110_0101 443: jmp cc_gtu, loop4 016D : 0000_0100_0000_0000_0000_1000 444: 445: ;################################# 446: ;# 447: ;# copy event buffer data of 448: ;# 449: ;################################# 450: 451: #ifdef cpu3 452: mov EBR5, r14 453: mov 66, r5 454: xor r3, c1, r3 455: 456: loop5: lpio+ r0 457: lpio+ r0 458: lpio+ r1 459: lpio r14, r2 460: 461: shl 10, r2, r2 462: or r1, r2, r2 463: shl 10, r2, r2 464: or r0, r2, r2 465: shl 2, r2, r2 466: or r3, r2, r2 467: 468: sra+ r2 469: 470: sub r5, c3, r5 471: jmp cc_gtu, loop5 472: #else 473: nop 016E : 0000_0000_0000_0000_0000_0000 474: nop 016F : 0000_0000_0000_0000_0000_0000 475: nop 0170 : 0000_0000_0000_0000_0000_0000 476: nop 0171 : 0000_0000_0000_0000_0000_0000 477: nop 0172 : 0000_0000_0000_0000_0000_0000 478: nop 0173 : 0000_0000_0000_0000_0000_0000 479: nop 0174 : 0000_0000_0000_0000_0000_0000 480: nop 0175 : 0000_0000_0000_0000_0000_0000 481: nop 0176 : 0000_0000_0000_0000_0000_0000 482: nop 0177 : 0000_0000_0000_0000_0000_0000 483: nop 0178 : 0000_0000_0000_0000_0000_0000 484: nop 0179 : 0000_0000_0000_0000_0000_0000 485: nop 017A : 0000_0000_0000_0000_0000_0000 486: nop 017B : 0000_0000_0000_0000_0000_0000 487: nop 017C : 0000_0000_0000_0000_0000_0000 488: nop 017D : 0000_0000_0000_0000_0000_0000 489: #endif 490: 491: 492: 493: ;################################# 494: ;# 495: ;# send all but cpu 3 to infi 496: ;# 497: ;################################# 498: 499: 500: 501: #ifdef cpu3 502: nop 503: #else 504: jmpr cc_uncond, 0 017E : 0000_0100_0010_1111_1100_1111 505: #endif 506: 507: nop 017F : 0000_0000_0000_0000_0000_0000 508: 509: 510: ;################################# 511: ;# 512: ;# increase counters (2/3) 513: ;# 514: ;################################# 515: 516: 517: mov 1, r1 0180 : 1100_0110_0000_0000_0010_0001 518: add r1, OFFSET_CTR, r0 0181 : 1000_0010_0001_0111_1000_0000 519: jmpr cc_busy, 0 0182 : 0000_0100_0011_0000_0101_0111 520: sgio r0, OFFSET_ADR 0183 : 0010_1000_0000_1100_0000_0100 521: 522: 523: 524: ;################################# 525: ;# 526: ;# Prepare Pedestal Follower 527: ;# 528: ;################################# 529: 530: 531: mov 0, r0 0184 : 1100_0110_0000_0000_0000_0000 532: iext EBSIM 0185 : 0101_0000_0000_0000_0000_0011 533: mov EBSIM, r1 0186 : 1100_0110_0000_0001_1010_0001 534: jmpr cc_busy, 0 0187 : 0000_0100_0011_0000_1111_0111 535: sgio r0, r1 0188 : 0010_0100_0000_0000_0010_0000 536: 537: mov 0, r0 0189 : 1100_0110_0000_0000_0000_0000 538: iext EBD 018A : 0101_0000_0000_0000_0000_0011 539: mov EBD, r1 018B : 1100_0110_0000_0001_0010_0001 540: jmpr cc_busy, 0 018C : 0000_0100_0011_0001_1001_0111 541: sgio r0, r1 018D : 0010_0100_0000_0000_0010_0000 542: 543: 544: mov 0, r6 ; r6: cha 018E : 1100_0110_0000_0000_0000_0110 545: mov 0, r7 ; r7: lim 018F : 1100_0110_0000_0000_0000_0111 546: iext FILCLK 0190 : 0101_0000_0000_0000_0000_0000 547: mov FILCLK, r8 ; r8: FIL 0191 : 1100_0111_0100_0101_0100_1000 548: mov 0, r9 ; r9: :=0 0192 : 1100_0110_0000_0000_0000_1001 549: mov 1, r10 ; r10: :=1 0193 : 1100_0110_0000_0000_0010_1010 550: iext 0x04000 0194 : 0101_0000_0000_0000_0000_0100 551: mov 0x04000, r11 ; r11: tim 0195 : 1100_0110_0000_0000_0000_1011 552: mov 0x010, r12 ; r12: tim 0196 : 1100_0110_0000_0010_0000_1100 553: mov 0, r13 ; r13: DBA 0197 : 1100_0110_0000_0000_0000_1101 554: iext FPA 0198 : 0101_0000_0000_0000_0000_0011 555: mov FPA, r14 ; r14: FPA 0199 : 1100_0110_0000_1100_0000_1110 556: iext 0xF000 019A : 0101_0000_0000_0000_0000_1111 557: mov 0xF000, r15 ; r15: DBA 019B : 1100_0110_0000_0000_0000_1111 558: 559: mov 1, r0 019C : 1100_0110_0000_0000_0010_0000 560: iext FPCL 019D : 0101_0000_0000_0000_0000_0011 561: mov FPCL, r1 019E : 1100_0110_0000_0100_0100_0001 562: jmpr cc_busy, 0 019F : 0000_0100_0011_0011_1111_0111 563: sgio r0, r1 ; activate 01A0 : 0010_0100_0000_0000_0010_0000 564: 565: 566: ;################################# 567: ;# 568: ;# Do Pedestal Follower Testi 569: ;# 570: ;# r0: time loop counter 571: ;# r1: value of channel 0 572: ;# r2: value of channel i 573: ;# r3: channel check loop 574: ;# r4: 575: ;# r5: DBANK write addres 576: ;# 577: ;################################# 578: 579: 580: dbkl: jmpr cc_busy, 0 01A1 : 0000_0100_0011_0100_0011_0111 581: sgio r10, r8 ; switch F 01A2 : 0010_0100_1010_0001_0000_0000 582: 583: mov r11, r0 ;################# 01A3 : 1100_0010_0000_0001_0110_0000 584: tmlp0: sub r0, c1, r0 ;# timing loop 01A4 : 1000_1010_0000_0110_0010_0000 585: jmp cc_geu, tmlp0 ;################# 01A5 : 0000_0100_0000_0000_0000_0000 586: nop 01A6 : 0000_0000_0000_0000_0000_0000 587: 588: jmpr cc_busy, 0 01A7 : 0000_0100_0011_0100_1111_0111 589: sgio r9, r8 ; switch F 01A8 : 0010_0100_1001_0001_0000_0000 590: 591: mov r12, r0 ;################# 01A9 : 1100_0010_0000_0001_1000_0000 592: tmlp1: sub r0, c1, r0 ;# Wait till FILCL 01AA : 1000_1010_0000_0110_0010_0000 593: jmp cc_geu, tmlp1 ;################# 01AB : 0000_0100_0000_0000_0000_0000 594: nop 01AC : 0000_0000_0000_0000_0000_0000 595: 596: iext FPA ;################# 01AD : 0101_0000_0000_0000_0000_0011 597: mov FPA, r14 ;# 01AE : 1100_0110_0000_1100_0000_1110 598: jmpr cc_busy, 0 ;# load FPA of cha 01AF : 0000_0100_0011_0101_1111_0111 599: lgio+ 0 ;# 01B0 : 1111_0100_0000_0000_0000_0000 600: jmpr cc_busy, 0 ;################# 01B1 : 0000_0100_0011_0110_0011_0111 601: lpio 0x300, r1 01B2 : 1110_0110_0110_0000_0000_0001 602: 603: mov 20, r3 ;################# 01B3 : 1100_0110_0000_0010_1000_0011 604: cclp: lgio+ 0 ;# 01B4 : 1111_0100_0000_0000_0000_0000 605: jmpr cc_busy, 0 ;# channel to chan 01B5 : 0000_0100_0011_0110_1011_0111 606: lpio 0x300, r2 ;# 01B6 : 1110_0110_0110_0000_0000_0010 607: ;# 608: cmp r2, r1 ;# do the com 01B7 : 1000_1000_0010_0000_0010_0000 609: jmp cc_eq, ccok ;# 01B8 : 0000_0100_0000_0000_0001_0001 610: add r6, c1, r6 ;# increase e 01B9 : 1000_0010_0110_0110_0010_0110 611: ;# 612: ccok: sub r3, c1, r3 ;# 01BA : 1000_1010_0011_0110_0010_0011 613: jmp cc_gtu, cclp ;################# 01BB : 0000_0100_0000_0000_0000_1000 614: 615: 616: add r13, r15, r5 ;################# 01BC : 1000_0010_1101_0001_1110_0101 617: jmpr cc_busy, 0 ;# store to DBANK 01BD : 0000_0100_0011_0111_1011_0111 618: sgio r1, r5 ;################# 01BE : 0010_0100_0001_0000_1010_0000 619: 620: add r13, c1, r13 ;################# 01BF : 1000_0010_1101_0110_0010_1101 621: cmp r13, 0x100 ;# loop ends after 01C0 : 1100_1000_1101_0001_0000_0000 622: jmp cc_ltu, dbkl ;################# 01C1 : 0000_0100_0000_0000_0001_0000 623: 624: nop 01C2 : 0000_0000_0000_0000_0000_0000 625: 626: 627: 628: ;################################# 629: ;# 630: ;# check limit value 631: ;# 632: ;# r1: received l 633: ;# r2: expected l 634: ;# 635: ;################################# 636: 637: 638: mov 255, r2 01C3 : 1100_0110_0001_1111_1110_0010 639: shl 13, r2, r2 01C4 : 1011_0010_1101_0000_0100_0010 640: shl 6, r2, r2 01C5 : 1011_0010_0110_0000_0100_0010 641: cmp r1, r2 01C6 : 1000_1000_0001_0000_0100_0000 642: jmp cc_eq, lvok 01C7 : 0000_0100_0000_0000_0001_0001 643: add r7, c1, r7 01C8 : 1000_0010_0111_0110_0010_0111 644: lvok: nop 01C9 : 0000_0000_0000_0000_0000_0000 645: 646: 647: 648: ;################################# 649: ;# 650: ;# cleanup after pedestal fil 651: ;# 652: ;################################# 653: 654: 655: clup: jmpr cc_busy, 0 01CA : 0000_0100_0011_1001_0101_0111 656: sgio r10, r8 ; switch F 01CB : 0010_0100_1010_0001_0000_0000 657: 658: jmpr cc_busy, 0 ; store ch 01CC : 0000_0100_0011_1001_1001_0111 659: sgio r6, CC_ERROR_ADR 01CD : 0010_1000_0110_1100_0000_0000 660: 661: jmpr cc_busy, 0 ; store li 01CE : 0000_0100_0011_1001_1101_0111 662: sgio r7, LV_ERROR_ADR 01CF : 0010_1000_0111_1100_0000_0001 663: 664: 665: 666: ;################################# 667: ;# 668: ;# increase counters (3/3) 669: ;# 670: ;################################# 671: 672: 673: mov 1024, r1 01D0 : 1100_0110_1000_0000_0000_0001 674: add r1, OFFSET_CTR, r0 01D1 : 1000_0010_0001_0111_1000_0000 675: jmpr cc_busy, 0 01D2 : 0000_0100_0011_1010_0101_0111 676: sgio r0, OFFSET_ADR 01D3 : 0010_1000_0000_1100_0000_0100 677: 678: 679: 680: ;################################# 681: ;# 682: ;# end current state, goto cl 683: ;# 684: ;################################# 685: 686: 687: 688: mov CMD_CLEAR, r0 01D4 : 1100_0110_1000_0010_0100_0000 689: jmpr cc_busy, 0 01D5 : 0000_0100_0011_1010_1011_0111 690: sgio r0, SMCMD 01D6 : 0010_1000_0000_1010_0000_0100 691: 692: 693: 694: ;################################# 695: ;# 696: ;# switch off own clock after 697: ;# 698: ;################################# 699: 700: 701: clkoff: mov 0, r0 01D7 : 1100_0110_0000_0000_0000_0000 702: jmpr cc_busy, 0 01D8 : 0000_0100_0011_1011_0001_0111 703: 704: #ifdef cpu0 705: sgio r0, CPU0SS 01D9 : 0010_1000_0000_1010_0010_0001 706: #endif 707: 708: #ifdef cpu1 709: sgio r0, CPU1SS 710: #endif 711: 712: #ifdef cpu2 713: sgio r0, CPU2SS 714: #endif 715: 716: #ifdef cpu3 717: sgio r0, CPU3SS 718: #endif 719: 720: jmp cc_uncond, clkoff 01DA : 0000_0100_0000_0000_0000_1111 721: nop 01DB : 0000_0000_0000_0000_0000_0000 722: 723: 724: 725: ;######################################### 726: ;# 727: ;# 0x0300: Interrrupt Raw Data Readou 728: ;# 729: ;# Nothing to be done here. 730: ;# 731: ;######################################### 732: 733: 734: org 0x300 735: 736: jmp cc_uncond, clkoff 0300 : 0000_0100_0000_0000_0000_1111 737: nop 0301 : 0000_0000_0000_0000_0000_0000 738: 739: 740: 741: 742: 743: 744: 745: 746: 747: 748: 749: 750: 751: 752: 753: 754: 755: 756: Source file read, 0 error(s), 0 warning(s).