-- trigger input stretch and output shorter
-- address "00 ": single register for enable/disable input stretch (0x0c00 = 3072) 
-- address "01 ": single register for enable/disable output shorter (0x0c01 = 3073)
-- write '0' ("00") to disable stretching 
-- write '1' ("01") to stretch  25ns puls to 50ns @ addr "00"
-- write '2' ("10") to stretch  25ns puls to 75ns @ addr "00"

library ieee;
use ieee.std_logic_1164.all;

entity trigger_input_stretch is
  
  port (
    clk40                     : in  std_logic;
    clkcpu                    : in  std_logic;
    reset_n                   : in  std_logic;
    we                        : in  std_logic;
    address                   : in  std_logic_vector(1 downto 0);
    trigger_input_stretch_IBO : in  std_logic_vector(31 downto 0);
    trigger_input_stretch_OBI : out std_logic_vector(31 downto 0);
    Sshort                    : in  std_logic_vector(575 downto 0);
    Slong                     : out std_logic_vector(575 downto 0);
    coinc_in                  : in  std_logic_vector(2 downto 0);
    coinc_out                 : out std_logic_vector(2 downto 0));
end trigger_input_stretch;

architecture behv of trigger_input_stretch is
  component signal_longer
    port (
      clk40   : in  std_logic;
      reset_n : in  std_logic;
      enable  : in  std_logic_vector(1 downto 0);
      bitin   : in  std_logic;
      bitout  : out std_logic);
  end component;

  component signal_shorter
    port (
      clk40   : in  std_logic;
      reset_n : in  std_logic;
      enable  : in  std_logic;
      bitin   : in  std_logic;
      bitout  : out std_logic);
  end component;

  signal enablein_cpu  : std_logic_vector(1 downto 0);
  signal enablein_40   : std_logic_vector(1 downto 0);
  signal enableout_cpu : std_logic;
  signal enableout_40  : std_logic;

  
begin  -- behv
-- Register to enable input stretch
  en_reg_p : process (clkcpu, reset_n)
  begin  -- process en_reg_p
    if reset_n = '0' then               -- asynchronous reset (active low)
      enablein_cpu <= "00";
    elsif clkcpu'event and clkcpu = '1' then  -- rising clock edge
      if address = "00" and we = '1' then
        enablein_cpu <= trigger_input_stretch_IBO(1 downto 0);
      end if;
    end if;
  end process en_reg_p;

-- sync to 40MHz
  process (clk40)
  begin  -- process
    if clk40'event and clk40 = '1' then  -- rising clock edge
      enablein_40 <= enablein_cpu;
    end if;
  end process;

-- instantiate 576 stretcher
  gen_longers : for i in 0 to 575 generate
    signal_longer_1 : signal_longer
      port map (
        clk40   => clk40,
        reset_n => reset_n,
        enable  => enablein_40,
        bitin   => Sshort(i),
        bitout  => Slong(i));
  end generate gen_longers;

-- Register to enable output reducer
  eno_reg_p : process (clkcpu, reset_n)
  begin  -- process eno_reg_p
    if reset_n = '0' then               -- asynchronous reset (active low)
      enableout_cpu <= '0';
    elsif clkcpu'event and clkcpu = '1' then  -- rising clock edge
      if address = "01" and we = '1' then
        enableout_cpu <= trigger_input_stretch_IBO(0);
      end if;
    end if;
  end process eno_reg_p;

-- sync to 40MHz
  process (clk40)
  begin  -- process
    if clk40'event and clk40 = '1' then  -- rising clock edge
      enableout_40 <= enableout_cpu;
    end if;
  end process;

-- instatntiate output reducer
  red_g: for i in 0 to 2 generate
    signal_shorter_1 : signal_shorter
      port map (
        clk40   => clk40,
        reset_n => reset_n,
        enable  => enableout_40,
        bitin   => coinc_in(i),
        bitout  => coinc_out(i));
    
  end generate red_g;

-- demux signals to be read back by SCSN
  with address select
    trigger_input_stretch_OBI <=
    (31 downto 2 => '0') & enablein_cpu  when "00",
    (31 downto 1 => '0') & enableout_cpu when "01",
    (31 downto 0 => '0')                 when others;
  
end behv;