-------------------------------------------------------------------------------
-- Title      : Testbench for design "tsserdes"
-- Project    : 
-------------------------------------------------------------------------------
-- File       : tsserdes_tb.vhd
-- Author     : tkrawuts
-- Company    : 
-- Created    : 2010-10-02
-- Last update: 2010-10-11
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2010 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2010-10-02  1.0      tkrawuts	Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------------------------------------

entity tsserdes_tb is

end tsserdes_tb;

-------------------------------------------------------------------------------

architecture dut of tsserdes_tb is


  
  component tsserdes
    generic (
      OutClockMultiplier : integer;
      OutClockDivisor    : integer;
      Oserdes_factor     : integer;
      parw               : integer;
      serw               : integer);
    port (
      reset_n : in  std_logic;
      clk     : in  std_logic;
      dclk    : out std_logic;
      dclkdiv : out std_logic;
      pardata : in  std_logic_vector(parw-1 downto 0);
      serdata : out std_logic_vector(serw-1 downto 0);
      start   : in  std_logic;
      done    : out std_logic);
  end component;

  -- component generics
  constant OutClockMultiplier : integer := 1;
  constant OutClockDivisor    : integer := 10;
  constant Oserdes_factor     : integer := 4;
  constant parw               : integer := 160; 
  constant serw               : integer := 8;

  constant p40  : time := 12500 ps;
  constant pdclk : time := p40*OutClockDivisor/OutClockMultiplier*Oserdes_factor;
  
  -- component ports
  signal reset_n : std_logic;
  signal clk     : std_logic;
  signal dclk    : std_logic;
  signal dclkdiv : std_logic;
  signal pardata : std_logic_vector(parw-1 downto 0);
  signal serdata : std_logic_vector(serw-1 downto 0);
  signal start   : std_logic;
  signal done    : std_logic;

  -- clock
  signal Clk40 : std_logic := '1';
  signal ddclk : std_logic := '1';

begin  -- dut

  -- component instantiation
  DUT: tsserdes
    generic map (
      OutClockMultiplier => OutClockMultiplier,
      OutClockDivisor    => OutClockDivisor,
      Oserdes_factor     => Oserdes_factor,
      parw               => parw,
      serw               => serw)
    port map (
      reset_n => reset_n,
      clk     => Clk40,
      dclk    => dclk,
      dclkdiv => dclkdiv,
      pardata => pardata,
      serdata => serdata,
      start   => start,
      done    => done);

  -- clock generation
  Clk40 <= not Clk40 after p40;
  ddclk <= not ddclk after pdclk;

  -- waveform generation
  WaveGen_Proc: process
  begin
    -- insert signal assignments here
    reset_n <= '0';
--    pardata <= (others => '0');
    pardata <= x"ffffffff" & x"1000000a" & x"2000000b" & x"30f6000c" & x"4000000d";
    start   <= '0';
    wait for pdclk*2;
    reset_n <= '1';
    wait for pdclk*2*10;
    start <= '1';
    wait for pdclk*2;
    start <= '0';


    wait until done='1';
    start <= '1';
    wait for pdclk*2;
    wait until (dclkdiv'event and dclkdiv='1');
    start <= '0';



    
    wait;
  end process WaveGen_Proc;

  

end dut;

-------------------------------------------------------------------------------

configuration tsserdes_tb_dut_cfg of tsserdes_tb is
  for dut
  end for;
end tsserdes_tb_dut_cfg;

-------------------------------------------------------------------------------