-- Example OutClockMultiplier=1, OutClockDivisor=10, Oserdes_fdactor=4 means:
-- OSERDES runs 1:4, input frequency 1MHz, Output Frequency 4MHz.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;



library UNISIM;
use UNISIM.vcomponents.all;

entity tsdcm is
  generic (
    OutClockMultiplier : integer := 1;  -- 40MHz clock multiplied by to achieve output clock
    OutClockDivisor    : integer := 10;  -- 40MHz clock divided by to achieve output clock
    Oserdes_factor     : integer := 4);  -- OSERDES factor
  port (
    clk40    : in  std_logic;           -- 40 MHz clock
    rst      : in  std_logic;           -- 40 MHz clock
    psen     : in  std_logic;           -- pulse for start shift
    psincdec : in  std_logic;           -- 1:+ 0:-
    psdone   : out std_logic;
    locked   : out std_logic;
    dclk     : out std_logic;   -- data clock out (high speed) to OSERDES
    dclkdiv  : out std_logic);  -- data clock out (diviede) to OSERDES/FSM FIFO etc

end tsdcm;

architecture behv of tsdcm is

  -- Using two DCMs: 1.divi makes output freqeuency, 2. Divides by Oserdes_factor
  
  signal CLK0          : std_logic;
  signal fmake_to_divi : std_logic;

  signal divi_out_dclk    : std_logic;
  signal divi_out_dclkdiv : std_logic;

  
begin  -- behv

  BUFGinst1 : BUFG
    port map(
      O => dclk,
      I => divi_out_dclk);

  BUFGinst2 : BUFG
    port map(
      O => dclkdiv,
      I => CLK0);

  
  
  DCM_PS_inst : DCM_PS
    generic map (
      CLKDV_DIVIDE          => 2.0,  -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
      --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE          => OutClockDivisor,  -- Can be any interger from 1 to 32
      CLKFX_MULTIPLY        => OutClockMultiplier,  -- Can be any integer from 2 to 32
      CLKIN_DIVIDE_BY_2     => false,  -- TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD          => 25.0,  -- Specify period of input clock in ns from 1.25 to 1000.00
      CLKOUT_PHASE_SHIFT    => "VARIABLE_CENTER",  -- Specify phase shift mode of NONE, FIXED, 
      -- VARIABLE_POSITIVE, VARIABLE_CENTER or DIRECT
      CLK_FEEDBACK          => "1X",    -- Specify clock feedback of NONE or 1X
      DCM_AUTOCALIBRATION   => true,  -- DCM calibrartion circuitry TRUE/FALSE
      DCM_PERFORMANCE_MODE  => "MAX_SPEED",  -- Can be MAX_SPEED or MAX_RANGE
      DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",  -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                        --   an integer from 0 to 15
      DFS_FREQUENCY_MODE    => "LOW",  -- HIGH or LOW frequency mode for frequency synthesis
      DLL_FREQUENCY_MODE    => "LOW",  -- LOW, HIGH, or HIGH_SER frequency mode for DLL
      DUTY_CYCLE_CORRECTION => true,    -- Duty cycle correction, TRUE or FALSE
      FACTORY_JF            => X"F0F0",  -- FACTORY JF Values Suggested to be set to X"F0F0" 
      PHASE_SHIFT           => 0,  -- Amount of fixed phase shift from -255 to 1023
      STARTUP_WAIT          => false)  -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
    port map (
      CLK0     => CLK0,     -- 0 degree DCM CLK ouptput
      CLK180   => open,                 -- 180 degree DCM CLK output
      CLK270   => open,                 -- 270 degree DCM CLK output
      CLK2X    => open,                 -- 2X DCM CLK output
      CLK2X180 => open,                 -- 2X, 180 degree DCM CLK out
      CLK90    => open,                 -- 90 degree DCM CLK output
      CLKDV    => open,                 -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX    => divi_out_dclk,        -- DCM CLK synthesis out (M/D)
      CLKFX180 => open,                 -- 180 degree CLK synthesis out
      DO       => open,  -- 16-bit data output for Dynamic Reconfiguration Port (DRP)
      LOCKED   => locked,                 -- DCM LOCK status output
      PSDONE   => PSDONE,                 -- Dynamic phase adjust done output
      CLKFB    => CLK0,     -- DCM clock feedback
      CLKIN    => clk40,           -- Clock input (from IBUFG, BUFG or DCM)
      PSCLK    => clk40,                -- Dynamic phase adjust clock input
      PSEN     => PSEN,                 -- Dynamic phase adjust enable input
      PSINCDEC => PSINCDEC,        -- Dynamic phase adjust increment/decrement
      RST      => rst                   -- DCM asynchronous reset input
      );











end behv;