------------------------------------------------------------------------------- -- Title : Testbench for design "tlmusend" -- Project : ------------------------------------------------------------------------------- -- File : tlmusend_tb.vhd -- Author : Tobias Krawutschke -- Company : -- Created : 2010-10-11 -- Last update: 2011-09-05 -- Platform : -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2010 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2010-10-11 1.0 tkrawuts Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- entity tlmusend_tb is end tlmusend_tb; ------------------------------------------------------------------------------- architecture dut of tlmusend_tb is component tlmusend generic ( OutClockMultiplier : integer; OutClockDivisor : integer; Oserdes_factor : integer; serw : integer); port ( clk40 : in std_logic; reset_n : in std_logic; Tin : in std_logic_vector(31 downto 0); Tout : out std_logic_vector(serw-1 downto 0); senddata : in std_logic_vector(575 downto 0); simdata : in std_logic_vector(575 downto 0); time_counter : in std_logic_vector(47 downto 0); start : in std_logic; active : out std_logic; address : in std_logic_vector(3 downto 0); we : in std_logic; tlmusend_IBO : in std_logic_vector(31 downto 0); tlmusend_OBI : out std_logic_vector(31 downto 0)); end component; component cbbr_top generic ( clkratio : integer); port ( clk40 : in std_logic; reset_n : in std_logic; address : in std_logic_vector(3 downto 0); cbbr_IBO : in std_logic_vector(31 downto 0); cbbr_OBI : out std_logic_vector(31 downto 0); we : in std_logic; ack : out std_logic; req : in std_logic; din : in std_logic_vector(7 downto 0); dinf : in std_logic_vector(7 downto 0); do : out std_logic_vector(31 downto 0); do_strobe : out std_logic); end component; -- component generics constant OutClockMultiplier : integer := 4; constant OutClockDivisor : integer := 1; constant Oserdes_factor : integer := 4; constant serw : integer := 8; constant p40 : time := 12500 ps; constant p80 : time := 6250 ps; constant pdclk : time := p40*OutClockDivisor/OutClockMultiplier*Oserdes_factor; -- component ports signal reset_n : std_logic; signal Tin : std_logic_vector(31 downto 0); signal Tout : std_logic_vector(serw-1 downto 0); signal senddata : std_logic_vector(575 downto 0); signal simdata : std_logic_vector(575 downto 0); signal time_counter : std_logic_vector(47 downto 0); signal start : std_logic; signal active : std_logic; signal address : std_logic_vector(3 downto 0); signal we : std_logic; signal tlmusend_IBO : std_logic_vector(31 downto 0); signal tlmusend_OBI : std_logic_vector(31 downto 0); -- clock signal Clk40 : std_logic := '1'; signal Clk80 : std_logic := '1'; signal Clk80n : std_logic ; signal ddclk : std_logic := '1'; -- cbbr signal signal cbbr_reset_n : std_logic; signal cbbr_address : std_logic_vector(3 downto 0); signal cbbr_IBO : std_logic_vector(31 downto 0); signal cbbr_OBI : std_logic_vector(31 downto 0); signal cbbr_we : std_logic; signal cbbr_ack : std_logic; signal cbbr_req : std_logic; signal cbbr_din : std_logic_vector(7 downto 0); signal cbbr_dinf : std_logic_vector(7 downto 0); signal do : std_logic_vector(31 downto 0); signal do_strobe : std_logic; begin -- dut -- component instantiation DUT : tlmusend generic map ( OutClockMultiplier => OutClockMultiplier, OutClockDivisor => OutClockDivisor, Oserdes_factor => Oserdes_factor, serw => serw) port map ( clk40 => Clk40, reset_n => reset_n, Tin => Tin, Tout => Tout, senddata => senddata, simdata => simdata, time_counter => time_counter, start => start, active => active, address => address, we => we, tlmusend_IBO => tlmusend_IBO, tlmusend_OBI => tlmusend_OBI); cbbr_top_1 : cbbr_top generic map ( clkratio => OutClockDivisor) port map ( clk40 => Clk80, reset_n => cbbr_reset_n, address => cbbr_address, cbbr_IBO => cbbr_IBO, cbbr_OBI => cbbr_OBI, we => cbbr_we, ack => cbbr_ack, req => cbbr_req, din => cbbr_din, dinf => cbbr_dinf, do => do, do_strobe => do_strobe); -- clock generation Clk40 <= not Clk40 after p40; Clk80 <= not Clk80 after p80; ddclk <= not ddclk after pdclk; Clk80n <= not Clk80; ddr: process (clk80) variable nege : std_logic_vector(7 downto 0); begin -- process ddr if clk80'event and clk80='1' then -- rising clock edge cbbr_din <= Tout; cbbr_dinf <= nege; end if; if clk80'event and clk80='0' then -- rising clock edge nege := Tout; -- cbbr_dinf <= Tout; end if; end process ddr; -- waveform generation WaveGen_Proc : process begin cbbr_reset_n <= '0'; cbbr_address <= "0000"; cbbr_IBO <= x"00000000"; cbbr_we <= '0'; cbbr_req <= '0'; reset_n <= '0'; Tin <= x"00000000"; senddata <= x"00000001" & x"00000002" & x"00000003" & x"00000004" & x"00000005" & x"00000006" & x"00000007" & x"00000008" & x"00000009" & x"0000000a" & x"0000000b" & x"0000000c" & x"0000000d" & x"0000000e" & x"0000000f" & x"00000010" & x"00000011" & x"00000012"; simdata <= x"10000001" & x"20000002" & x"30000003" & x"40000004" & x"50000005" & x"60000006" & x"70000007" & x"80000008" & x"90000009" & x"a000000a" & x"b000000b" & x"c000000c" & x"d000000d" & x"e000000e" & x"f000000f" & x"10000010" & x"11000011" & x"12000012"; time_counter <= x"12345678abcd"; start <= '0'; address <= "0000"; we <= '0'; tlmusend_IBO <= x"00000000"; wait for 2*pdclk; reset_n <= '1'; cbbr_reset_n <= '1'; wait for 20*pdclk; wait for 20*pdclk; Tin <= x"00000001"; wait for 2*p40; Tin <= x"00000000"; wait for 2*p40; -- read FIFO Write count address <= x"3"; wait for 2*p40; -- read FIFO Flags address <= x"4"; wait for 2*p40; -- set trigger src to bit 16 we <= '1'; address <= "0000"; tlmusend_IBO <= x"00000010"; wait for 2*p40; we <= '0'; wait for 2*p40; Tin <= x"00010000"; wait for 2*p40; Tin <= x"00000000"; wait for 2*p40; -- read FIFO Write count address <= x"3"; wait for 2*p40; -- read FIFO Flags address <= x"4"; wait for 2*p40; -- set trigger src to bit 0, data src to simdata, then send trigger pulse via SCSN we <= '1'; address <= "0000"; tlmusend_IBO <= x"00000020"; wait for 2*p40; we <= '0'; wait for 2*p40; we <= '1'; address <= "0001"; tlmusend_IBO <= x"00000000"; wait for 2*p40; we <= '0'; wait for 2*p40; simdata <= x"10001001" & x"20002002" & x"30030003" & x"40000404" & x"50500005" & x"60060006" & x"70007007" & x"80080008" & x"90009009" & x"a0000a0a" & x"b0000b0b" & x"c0000c0c" & x"d000d00d" & x"e000e00e" & x"f000f00f" & x"10010010" & x"11011011" & x"12012012"; we <= '1'; address <= "0001"; tlmusend_IBO <= x"00000000"; wait for 2*p40; we <= '0'; wait for 2*p40; -- activate cbbr receiver cbbr_we <= '1'; cbbr_address <= "0000"; cbbr_IBO <= x"00000001"; wait for 2*p40; cbbr_we <= '0'; wait for 2*p40; -- TEST tst_mode ot send x*y packets -- number of FIFO loads to addres 6 we <= '1'; address <= "0110"; tlmusend_IBO <= x"00000004"; wait for 2*p40; we <= '0'; wait for 2*p40; -- number of cycles to Address 7 we <= '1'; address <= "0111"; tlmusend_IBO <= x"00000002"; wait for 2*p40; we <= '0'; wait for 2*p40; -- start we <= '1'; address <= "1000"; tlmusend_IBO <= x"00000000"; wait for 2*p40; we <= '0'; wait for 2*p40; -- external started wait for 30 us; -- start send start <= '1'; wait for 2*pdclk; start <= '0'; wait until (active'event and active = '0'); wait for 2*pdclk; start <= '1'; wait for 2*pdclk; start <= '0'; wait until (active'event and active = '0'); -- set crc spoil bit we <= '1'; address <= "0101"; tlmusend_IBO <= x"00000001"; wait for 2*p40; we <= '0'; wait for 2*p40; wait for 2*pdclk; start <= '1'; wait for 2*pdclk; start <= '0'; wait until (active'event and active = '0'); -- unset crc spoil bit we <= '1'; address <= "0101"; tlmusend_IBO <= x"00000000"; wait for 2*p40; we <= '0'; wait for 2*p40; wait for 2*pdclk; start <= '1'; wait for 2*pdclk; start <= '0'; wait until (active'event and active = '0'); wait for 20*p40; cbbr_address <= "0001"; wait for 2*p40; cbbr_address <= "0010"; wait for 2*p40; cbbr_we <= '1'; cbbr_address <= "0001"; wait for 2*p40; cbbr_we <= '0'; wait for 2*p40; cbbr_we <= '1'; cbbr_address <= "0010"; wait for 2*p40; cbbr_we <= '0'; wait for 2*p40; cbbr_address <= "0001"; wait for 2*p40; cbbr_address <= "0010"; wait for 2*p40; wait; end process WaveGen_Proc; end dut; ------------------------------------------------------------------------------- configuration tlmusend_tb_dut_cfg of tlmusend_tb is for dut end for; end tlmusend_tb_dut_cfg; -------------------------------------------------------------------------------