-- simple syncs between fast and slow clk:
-- a single high pulse sync to fastclk posedge generates a single high puls sync
-- to slow clk

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity clksync is
  
  port (
    reset_n : in  std_logic;
    fastclk : in  std_logic;
    slowclk : in  std_logic;
    fastin  : in  std_logic;
    slowout : out std_logic);

end clksync;

architecture behv of clksync is

  signal interclk : std_logic;
  signal slowout_i : std_logic;

begin  -- behv

  fastc: process (fastclk, reset_n)
  begin  -- process fastc
    if reset_n = '0' then               -- asynchronous reset (active low)
      interclk <= '0';
    elsif fastclk'event and fastclk = '1' then  -- rising clock edge
      if fastin = '1' then
        interclk <= '1';
      elsif slowout_i = '1' then
        interclk <= '0';
      end if;
    end if;
  end process fastc;

  slowc: process (slowclk, reset_n)
  begin  -- process slowc
    if reset_n = '0' then               -- asynchronous reset (active low)
      slowout_i <= '0';
    elsif slowclk'event and slowclk = '1' then  -- rising clock edge
      slowout_i <= interclk;
    end if;
  end process slowc;

  slowout <= slowout_i;
  
end behv;