-- sorerorcnt.vhd
-- SOR /EOR Counter: 48 Bit counter to measure run length
-- starts with 0 at SOR, stops and hold at EOR
-- Snapshot during run: write anything to address 0x3400 to latch value
-- Then read from 0x3401  Bits 31..0
-- then read from 0x3402 Bits 47..32
-- Reset: write anything to address 0x3403

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity soreorcnt is
  
  port (
    cntclk    : in  std_logic;
    cpuclk    : in  std_logic;
    reset_n   : in  std_logic;
    soreor    : in  std_logic;
    address   : in  std_logic_vector(1 downto 0);
    we        : in  std_logic;
    cntout    : out std_logic_vector(47 downto 0);
    secnt_IBO : in  std_logic_vector(31 downto 0);
    secnt_OBI : out std_logic_vector(31 downto 0)
    );

end soreorcnt;

architecture behv of soreorcnt is

 signal counter : std_logic_vector(47 downto 0);
 signal latch : std_logic_vector(47 downto 0);

 signal cnt_clr,cnt_clr_cpu : std_logic;

 signal snap,snap_cpu : std_logic;
 
begin  -- behv

  -- sync CPUclk to Cnt clk for clear
  cpuclk_cntclr_p: process (cpuclk, reset_n)
  begin  -- process cpuclk_cntclr_p
    if reset_n = '0' then               -- asynchronous reset (active low)
      cnt_clr_cpu <= '0';
    elsif cpuclk'event and cpuclk = '1' then  -- rising clock edge
      if address = "11" and we = '1' then
        cnt_clr_cpu <= '1';
      elsif cnt_clr = '1' then
        cnt_clr_cpu <= '0';
      end if;
    end if;
  end process cpuclk_cntclr_p;

  cntclk_cntclr_p: process (cntclk, reset_n)
  begin  -- process cntclk_cntclr_p
    if reset_n = '0' then               -- asynchronous reset (active low)
      cnt_clr <= '0';
    elsif cntclk'event and cntclk = '1' then  -- rising clock edge
      cnt_clr <= cnt_clr_cpu;
    end if;
  end process cntclk_cntclr_p;


  -- sync CPUclk ro Cnt clk for latch
  snap_cpu_p: process (cpuclk, reset_n)
  begin  -- process snap_cpu_p
    if reset_n = '0' then               -- asynchronous reset (active low)
      snap_cpu <= '0';
    elsif cpuclk'event and cpuclk = '1' then  -- rising clock edge
      if  address = "00" and we = '1' then
        snap_cpu <= '1';
      elsif snap = '1' then
        snap_cpu <= '0';
      end if;
    end if;
  end process snap_cpu_p;
  snap_p: process (cntclk, reset_n)
  begin  -- process snap_p
    if reset_n = '0' then               -- asynchronous reset (active low)
      snap <= '0';
    elsif cntclk'event and cntclk = '1' then  -- rising clock edge
      snap <= snap_cpu;
    end if;
  end process snap_p;
  
  -- COUNTER
  cnt: process (cntclk, reset_n)
  begin  -- process cnt
    if reset_n = '0' then               -- asynchronous reset (active low)
      counter <= (others => '0');
    elsif cntclk'event and cntclk = '1' then  -- rising clock edge
      if cnt_clr = '1' then
        counter <= (others => '0');
      elsif soreor='1' then
        counter <= counter + 1;
      end if;
    end if;
  end process cnt;

  cntout <= counter;
  
  -- Register to LATCH
  latch_p: process (cntclk, reset_n)
  begin  -- process latch_p
    if reset_n = '0' then               -- asynchronous reset (active low)
      latch <= (others => '0');
    elsif cntclk'event and cntclk = '1' then  -- rising clock edge
      if snap = '1' then
        latch <= counter;
      end if;
    end if;
  end process latch_p;
  

  with address select
    secnt_OBI <=
    latch(31 downto 0)  when "01",
    ((15 downto 0 => '0') & latch(47 downto 32)) when others;

end behv;