-- if enable "01" , a 25ns puls at bitin wil be outputted as 50ns puls
-- if enable "10" , a 25ns puls at bitin wil be outputted as 75ns puls

library ieee;
use ieee.std_logic_1164.all;

entity signal_longer is
  
  port (
    clk40   : in  std_logic;
    reset_n : in  std_logic;
    enable  : in  std_logic_vector(1 downto 0);
    bitin   : in  std_logic;
    bitout  : out std_logic);

end signal_longer;

architecture behv of signal_longer is

 signal r : std_logic_vector(1 downto 0);

begin  -- behv

reg_p: process (clk40, reset_n)
  begin  -- process reg_p
    if reset_n = '0' then               -- asynchronous reset (active low)
      r <= "00";
    elsif clk40'event and clk40 = '1' then  -- rising clock edge
      r <= r(0) & bitin;                -- shift left
    end if;
  end process reg_p;  

  with enable select
    bitout <=
    (r(0) or bitin) when "01",
    (r(1) or r(0) or bitin) when "10",
    bitin      when others;
  
end behv;