-- Output switch
-- 8 Trigger Outputs
-- 32 Trigger Inputs
-- select for each ouptut (Address 0..7)
-- which input to select (0..31 = 5 Bit)
--
-- Reset: Output 7..0 are mapped to input 7..0
-- Added delay to each output, reset 0 BCs

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity output_switch is
  
  port (
    cpuclk      : in  std_logic;
    clk40       : in  std_logic;    
    reset_n     : in  std_logic;
    oswitch_IBO : in  std_logic_vector(31 downto 0);
    oswitch_OBI : out std_logic_vector(31 downto 0);
    we          : in  std_logic;
    address     : in  std_logic_vector(3 downto 0);
    Tout        : out std_logic_vector(7 downto 0);
    Tin         : in  std_logic_vector(31 downto 0));

end output_switch;

architecture behv of output_switch is


  subtype reg_st is std_logic_vector(4 downto 0);
  subtype del_st is std_logic_vector(1 downto 0);
  subtype stage_st is std_logic_vector(3 downto 0);
  type reg_arr is array(0 to 7) of reg_st;
  type del_arr is array(0 to 7) of del_st;
  type stage_arr is array(0 to 7) of stage_st;

  -- The 8 mapping registers
  signal reg   : reg_arr;

  -- The 8 delay registers
  signal del   : del_arr;

  -- The 8 delay stages
  signal stage : stage_arr;
  
begin  -- behv

  -- Register set
  reg_gen : for i in 0 to 7 generate
    ii : process (cpuclk, reset_n)
    begin  -- process ii
      if reset_n = '0' then             -- asynchronous reset (active low)
        reg(i) <= conv_std_logic_vector(i, 5);
        del(i) <= "00";
      elsif cpuclk'event and cpuclk = '1' then  -- rising clock edge
        if conv_integer(address(2 downto 0)) = i and we = '1' then
          if address(3) = '0' then
            reg(i) <= oswitch_IBO(4 downto 0);
          else
            del(i) <= oswitch_IBO(1 downto 0);
          end if;
        end if;
      end if;
    end process ii;

    -- Multiplexer zero delay stage;
    stage(i)(0) <= Tin(conv_integer(reg(i)));

    
    
    stager: process (clk40, reset_n)
    begin  -- process stager
      if reset_n = '0' then             -- asynchronous reset (active low)
        stage(i)(3 downto 1) <= "000";
      elsif clk40'event and clk40 = '1' then  -- rising clock edge
        stage(i)(3 downto 1) <= stage(i)(2 downto 0);
      end if;
    end process stager;

    -- Ouput: seleted delay stage
    Tout(i) <= stage(i)(conv_integer(del(i)));
    
  end generate reg_gen;



  adre : process (reg, address)
  begin  -- process adre
    if address(3) = '0' then
      oswitch_OBI <= (31 downto 5 => '0') & reg(conv_integer(address(2 downto 0)));
    else
      oswitch_OBI <= (31 downto 2 => '0') & del(conv_integer(address(2 downto 0)));
    end if;

  end process adre;


end behv;