-- Multiplicity unit: input: 576 signals , output 10 Bit (0..575) containig
-- multiplicity value. oreg registers output. For pipelines set register in
-- Adder64x2in. Comments in source suggest other register inbeetween adder
-- stages.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity multi is
  generic (
    oreg : boolean := true);
  port (
    clk     : in  std_logic;
    reset_n : in  std_logic;
    invec   : in  std_logic_vector(575 downto 0);
    outvec  : out std_logic_vector(9 downto 0));

end multi;

architecture behv of multi is

  constant l1reg : boolean := false;
  constant l2reg : boolean := false;
  constant l3reg : boolean := true;
  constant l4reg : boolean := false;
  constant l5reg : boolean := false;
  constant l6reg : boolean := false;

  component Adder64x2in_8out
    generic (
      l1reg : boolean;
      l2reg : boolean;
      l3reg : boolean;
      l4reg : boolean;
      l5reg : boolean;
      l6reg : boolean);
    port (
      clk     : in  std_logic;
      reset_n : in  std_logic;
      invec   : in  std_logic_vector(127 downto 0);
      outvec  : out std_logic_vector(7 downto 0));
  end component;

  component cntonesLUT3
    port (
      invec  : in  std_logic_vector(2 downto 0);
      outvec : out std_logic_vector(1 downto 0));
  end component;

  -- count ones with LUT 3 192 times, two signal for optional register
  signal l0out : std_logic_vector(383 downto 0);
  signal l1in  : std_logic_vector(383 downto 0);

  subtype add64_out_st is std_logic_vector(7 downto 0);
  type add64_out_t is array(0 to 2) of add64_out_st;
  signal add64_out : add64_out_t;

  signal l7out : std_logic_vector(8 downto 0);
  signal l8in  : std_logic_vector(8 downto 0);
  signal l8out : std_logic_vector(9 downto 0);
  
begin  -- behv


  -- Instantioate 193 x LUT3 to count the ones
  cntones_gen : for i in 0 to 191 generate
    cntonesLUT3_i : cntonesLUT3
      port map (
        invec  => invec(i*3+2 downto i*3+0),
        outvec => l0out(i*2+1 downto i*2+0)
        );
  end generate cntones_gen;

  -- May register
  l1in <= l0out;

  -- 3 64 Bit adder
  add64_gen : for i in 0 to 2 generate
    Adder64x2in_8out_1 : Adder64x2in_8out
      generic map (
        l1reg => l1reg,
        l2reg => l2reg,
        l3reg => l3reg,
        l4reg => l4reg,
        l5reg => l5reg,
        l6reg => l6reg)
      port map (
        clk     => clk,
        reset_n => reset_n,
        invec   => l1in(i*128+127 downto i*128),
        outvec  => add64_out(i)
        );
  end generate add64_gen;

  -- l7out: 9wide   add64: 8 wide
  l7out <= ('0' & add64_out(2)) + ('0' & add64_out(1));

  -- May register
  l8in <= l7out;

          -- l8out: 10wide
 l8out <= ('0' & l7out) + ("00" & add64_out(0));


  oreg_g : if oreg generate
    oreg_p : process (clk, reset_n)
    begin  -- process l1reg_p
      if reset_n = '0' then               -- asynchronous reset (active low)
        outvec <= (others => '0');
      elsif clk'event and clk = '1' then  -- rising clock edge
        outvec <= l8out;
      end if;
    end process oreg_p;
  end generate oreg_g;

  noreg_g : if not oreg generate
    outvec <= l8out;
  end generate noreg_g;

end behv;


-------------------------------------------------------------------------------
-- All registers except oreg turned off:
--
--
--
--  Device utilization summary:
--  ---------------------------
--  
--  Selected Device : 4vlx40ff1148-11 
--  
--   Number of Slices:                     612  out of  18432     3%  
--   Number of 4 input LUTs:              1063  out of  36864     2%  
--   Number of IOs:                        588
--   Number of bonded IOBs:                588  out of    640    91%  
--      IOB Flip Flops:                     10
--   Number of GCLKs:                        1  out of     32     3%
--
-- **************************
-- Generating Clock Report
-- **************************
-- 
-- +---------------------+--------------+------+------+------------+-------------+
-- |        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
-- +---------------------+--------------+------+------+------------+-------------+
-- |           clk_BUFGP |BUFGCTRL_X0Y20| No   |   10 |  0.044     |  2.412      |
-- +---------------------+--------------+------+------+------------+-------------+
-- 
-- * Net Skew is the difference between the minimum and maximum routing
-- only delays for the net. Note this is different from Clock Skew which
-- is reported in TRCE timing report. Clock Skew is the difference between
-- the minimum and maximum path delays which includes logic delays.
-- 
-- 
--    The Delay Summary Report
-- 
-- 
-- The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
-- 
--    The AVERAGE CONNECTION DELAY for this design is:        0.745
--    The MAXIMUM PIN DELAY IS:                               2.412
--    The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.125
-- 
--    Listing Pin Delays by value: (nsec)
-- 
--     d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
--    ---------   ---------   ---------   ---------   ---------   ---------
--         2753         850          22           0           0           0
--