-------------------------------------------------------------------------------
-- 64x2 inputs = 128 Bit input vector --> 8 Bit output vector
-- 2 inputs = maximum number: 3 3*64 = 192 fits in 8 Bit
-- hierarchical approach:
-- 32 Adder 2 in 3 out -- Layer 1
-- 16 Adder 3 in 4 out -- Layer 2
--  8 Adder 4 in 5 out -- Layer 3
--  4 Adder 5 in 6 out -- Layer 4
--  2 Adder 6 in 7 out -- Layer 5
--  1 Adder 7 in 8 out -- Layer 6
-- optional register per Layer
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity Adder64x2in_8out is
  generic(
    l1reg : boolean := false;           -- Register Level 1 Adder output
    l2reg : boolean := false;           -- Register Level 2 Adder output
    l3reg : boolean := false;           -- Register Level 3 Adder output
    l4reg : boolean := false;           -- Register Level 4 Adder output
    l5reg : boolean := false;           -- Register Level 5 Adder output
    l6reg : boolean := true);          -- Register Level 6 Adder output
  port (
    clk     : in  std_logic;
    reset_n : in  std_logic;
    invec   : in  std_logic_vector(127 downto 0);
    outvec  : out std_logic_vector(7 downto 0));

end Adder64x2in_8out;

architecture behv of Adder64x2in_8out is

  signal l1out : std_logic_vector(95 downto 0);  -- 32x3 = 96
  signal l2in  : std_logic_vector(95 downto 0);

  signal l2out : std_logic_vector(63 downto 0);  -- 16x4 = 64
  signal l3in  : std_logic_vector(63 downto 0);

  signal l3out : std_logic_vector(39 downto 0);  -- 8x5 = 40
  signal l4in  : std_logic_vector(39 downto 0);

  signal l4out : std_logic_vector(23 downto 0);  -- 4x6 = 24
  signal l5in  : std_logic_vector(23 downto 0);

  signal l5out : std_logic_vector(13 downto 0);  -- 2x7 = 14
  signal l6in  : std_logic_vector(13 downto 0);  -- 2x7 = 14

  signal l6out : std_logic_vector(7 downto 0);  -- 1x8 = 8
  signal l7in  : std_logic_vector(7 downto 0);
  
begin  -- behv

  l1adder : for i in 0 to 31 generate
    l1out(i*3 + 2 downto i*3) <= ('0' & invec(i*4+3 downto i*4+2)) + ('0' & invec(i*4+1 downto i*4+0));
  end generate l1adder;

  l2adder : for i in 0 to 15 generate
    l2out(i*4 + 3 downto i*4) <= ('0' & l2in(i*6+5 downto i*6+3)) + ('0' & l2in(i*6+2 downto i*6+0));
  end generate l2adder;

  l3adder : for i in 0 to 7 generate
    l3out(i*5 + 4 downto i*5) <= ('0' & l3in(i*8+7 downto i*8+4)) + ('0' & l3in(i*8+3 downto i*8+0));
  end generate l3adder;

  l4adder : for i in 0 to 3 generate
    l4out(i*6 + 5 downto i*6) <= ('0' & l4in(i*10+9 downto i*10+5)) + ('0' & l4in(i*10+4 downto i*10+0));
  end generate l4adder;

  l5adder : for i in 0 to 1 generate
    l5out(i*7 + 6 downto i*7) <= ('0' & l5in(i*12+11 downto i*12+6)) + ('0' & l5in(i*12+5 downto i*12+0));
  end generate l5adder;

  -- A single l6adder:
  l6out <= ('0' & l6in(13 downto 7)) + ('0' & l6in(6 downto 0));

  -- Register levelstages depending on generic
  -- Layer 1 output
  l1reg_g : if l1reg generate
    l1reg_p : process (clk, reset_n)
    begin  -- process l1reg_p
      if reset_n = '0' then               -- asynchronous reset (active low)
        l2in <= (others => '0');
      elsif clk'event and clk = '1' then  -- rising clock edge
        l2in <= l1out;
      end if;
    end process l1reg_p;
  end generate l1reg_g;

  -- Layer 2 output
  l2reg_g : if l2reg generate
    l2reg_p : process (clk, reset_n)
    begin  -- process l2reg_p
      if reset_n = '0' then               -- asynchronous reset (active low)
        l3in <= (others => '0');
      elsif clk'event and clk = '1' then  -- rising clock edge
        l3in <= l2out;
      end if;
    end process l2reg_p;
  end generate l2reg_g;

  -- Layer 3 output
  l3reg_g : if l3reg generate
    l3reg_p : process (clk, reset_n)
    begin  -- process l3reg_p
      if reset_n = '0' then               -- asynchronous reset (active low)
        l4in <= (others => '0');
      elsif clk'event and clk = '1' then  -- rising clock edge
        l4in <= l3out;
      end if;
    end process l3reg_p;
  end generate l3reg_g;

  -- Layer 4 output
  l4reg_g : if l4reg generate
    l4reg_p : process (clk, reset_n)
    begin  -- process l4reg_p
      if reset_n = '0' then               -- asynchronous reset (active low)
        l5in <= (others => '0');
      elsif clk'event and clk = '1' then  -- rising clock edge
        l5in <= l4out;
      end if;
    end process l4reg_p;
  end generate l4reg_g;

  -- Layer 5 output
  l5reg_g : if l5reg generate
    l5reg_p : process (clk, reset_n)
    begin  -- process l5reg_p
      if reset_n = '0' then               -- asynchronous reset (active low)
        l6in <= (others => '0');
      elsif clk'event and clk = '1' then  -- rising clock edge
        l6in <= l5out;
      end if;
    end process l5reg_p;
  end generate l5reg_g;

  -- Layer 6 output
  l6reg_g : if l6reg generate
    l6reg_p : process (clk, reset_n)
    begin  -- process l6reg_p
      if reset_n = '0' then               -- asynchronous reset (active low)
        l7in <= (others => '0');
      elsif clk'event and clk = '1' then  -- rising clock edge
        l7in <= l6out;
      end if;
    end process l6reg_p;
  end generate l6reg_g;

  -- Do not register outputs dependent on generic
  l1noreg_g : if not l1reg generate
    l2in <= l1out;
  end generate l1noreg_g;

  l2noreg_g : if not l2reg generate
    l3in <= l2out;
  end generate l2noreg_g;

  l3noreg_g : if not l3reg generate
    l4in <= l3out;
  end generate l3noreg_g;

  l4noreg_g : if not l4reg generate
    l5in <= l4out;
  end generate l4noreg_g;

  l5noreg_g : if not l5reg generate
    l6in <= l5out;
  end generate l5noreg_g;

  l6noreg_g : if not l6reg generate
    l7in <= l6out;
  end generate l6noreg_g;

  -- Map out
  outvec <= l7in;
  
end behv;

-------------------------------------------------------------------------------
-- Worst pin to  pin delay without any register: 19.731 ns
--
-- l6reg = true:
--   Listing Pin Delays by value: (nsec)
--
--    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
--   ---------   ---------   ---------   ---------   ---------   ---------
--         423         376          33           0           0           0