LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

entity waitstate is
  
  generic (
    cntwidth : integer := 3);

  port (
    clk     : in  std_logic;
    reset_n : in  std_logic;
    val     : in  std_logic_vector(cntwidth-1 downto 0);
    start   : in  std_logic;
    expired : out std_logic);

end waitstate;

architecture behv of waitstate is


  signal cntreg : std_logic_vector(cntwidth-1 downto 0);
  
begin  -- behv

  ws_cnt_p: process (clk, reset_n)
  begin  -- process ws_cnt_p
    if reset_n = '0' then               -- asynchronous reset (active low)
      cntreg <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if start = '0' then
        cntreg <= (others => '0');
      else
        cntreg <= cntreg + 1;
      end if;
    end if;
  end process ws_cnt_p;

  expired <= '1' when cntreg = (val - 1) else '0';
  
end behv;