LIBRARY IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

entity counter_block is
generic(Na   : Integer :=  8;
        Nbit : Integer := 32;
        shortpulse : boolean := false;
        areg : Boolean := true;
        qreg : Boolean := true);
port(
        clk     : in  std_logic;
        srst    : in  std_logic;
        glb_en  : in  std_logic;
        cntin   : in  std_logic_vector(2**Na-1 downto 0);
        raddr   : in  std_logic_vector(Na-1 downto 0);
        q       : out std_logic_vector(Nbit-1 downto 0));
end counter_block;

architecture a of counter_block is
component counter is
generic (N : Natural := 8);
port (
    clk    : in  std_logic;
    srst   : in  std_logic;
    cnten  : in  std_logic;
    q      : out std_logic_vector(N-1 downto 0) );
end component;

component cnt_sync is
generic (N : Integer := 3;
         shortpulse : boolean := false);
port(
     sysclk : in    std_logic;
     cntclk : in    std_logic;
     glb_en : in    std_logic;
     cnt_en : out   std_logic);
end component;

signal raddr_i : Integer range 0 to 2**raddr'length-1;

subtype cnt_out is std_logic_vector(Nbit-1 downto 0);
type    cnt_arr is array(0 to 2**raddr'length-1) of cnt_out;

signal counters : cnt_arr;
signal cnten    : std_logic_vector(0 to 2**raddr'length-1);

signal srst_r   : std_logic;
signal glb_en_r : std_logic;

begin

ra_reg : if areg generate
    process(clk)
    begin
        if rising_edge(clk) then
            raddr_i <= conv_integer(raddr);
            srst_r  <= srst;
            glb_en_r <= glb_en;
        end if;
    end process;
end generate;

ra_dir : if not areg generate
    raddr_i <= conv_integer(raddr);
    srst_r  <= srst;
    glb_en_r <= glb_en;
end generate;

cnt: for i in 0 to 2**raddr'length-1 generate

sync: cnt_sync
generic map(N => 3,
         shortpulse => shortpulse)
port map(
     sysclk => clk,
     cntclk => cntin(i),
     glb_en => glb_en_r,
     cnt_en => cnten(i));

cnti: counter
generic map(N => Nbit)
port map(
    clk    => clk,
    srst   => srst_r,
    cnten  => cnten(i),
    q      => counters(i));

end generate;

q_reg : if qreg generate
    process(clk)
    begin
        if rising_edge(clk) then
            q <= counters(raddr_i);
        end if;
    end process;
end generate;

q_dir : if not qreg generate
    q <= counters(raddr_i);
end generate;

end;