LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

entity counter is
generic (N : Natural := 8);
port (
    clk    : in  std_logic;
    srst   : in  std_logic;
    cnten  : in  std_logic;
    q      : out std_logic_vector(N-1 downto 0) );
end counter;

architecture a of counter is
signal q_i    : std_logic_vector(q'range);
signal srst_s : std_logic;
begin
process(clk)
begin
    if clk'event and clk='1' then
        srst_s <= srst;
        if srst_s='1' then
            q_i    <= (others => '0');
        elsif cnten='1' then
            q_i <= q_i + 1;
        end if;
    end if;
end process;
q <= q_i;
end;