LIBRARY IEEE;
use IEEE.std_logic_1164.all;

entity cnt_sync is
generic (N : Integer := 3;
         shortpulse : boolean := false);
port(
     sysclk : in    std_logic;
     cntclk : in    std_logic;
     glb_en : in    std_logic;
     cnt_en : out   std_logic);
end cnt_sync;

architecture a of cnt_sync is
signal samples  : std_logic_vector(N-1 downto 0);
signal toggle   : std_logic;
begin
sp: if shortpulse generate
    process(cntclk)
    begin
        if rising_edge(cntclk) then
            toggle <= not toggle;
        end if;
    end process;

    process(sysclk)
    begin
        if rising_edge(sysclk) then
            samples <= samples(samples'high-1 downto 0) & toggle;
            cnt_en  <= (samples(samples'high) xor samples(samples'high-1)) and glb_en;
        end if;
    end process;
end generate;

lp: if not shortpulse generate
    process(sysclk)
    begin
        if rising_edge(sysclk) then
            cnt_en  <= cntclk and glb_en;
        end if;
    end process;

end generate;

end;