library IEEE; use IEEE.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity cnt576x48 is port ( clk : in std_logic; cpuclk : in std_logic; reset_n : in std_logic; S : in std_logic_vector(575 downto 0); soreor : in std_logic; we : in std_logic; rd : in std_logic; address : in std_logic_vector(2 downto 0); counter_IBO : in std_logic_vector(31 downto 0); counter_OBI : out std_logic_vector(31 downto 0)); end cnt576x48; architecture bev of cnt576x48 is -- counterwidth depends on waitstates: currently -- counter mapping: -- areg,mreg,qreg affects waitstates in fsm: -- delay from address change, to q valid: -- areg mreg qreg -- 0 cycles ( 0 ns) @ false false false -- 2 cycles ( 50 ns) @ false false true -- 1 cycles ( 25 ns) @ false true false -- 3 cycles ( 75 ns) @ false true true -- 3 cycles ( 75 ns) @ true false false -- 5 cycles (125 ns) @ true false true -- 4 cycles (100 ns) @ true true false -- 6 cycles (150 ns) @ true true true -- edit fsm.vhd: ws_val <= -- ... -- "110" when en_wait_cntmux, -- (6 waitstates) -- "110" when dis_wait_cntmux, -- add above cycles + waitstate for calculate (min.1) + 3 -- example max 6 + 1 + 3 = 10 -- 10*576 = 5760 cycles: 2^12 (4096) < 5760 < 2^13 (8192) ----> counterwidth:=13 -- -- example min 1 + 1 + 3 = 5 -- 5*576 = 2880 cycles: 2^11 (2048) < 2880 < 2^12(4096) ----> counterwidth:=12 -- 7*576 = 4032, 12 also ok for 3 waitstates -- ideally: pipelined adding and storing using only 10 bit counterwidth constant counterwidth : integer := 12; constant areg : boolean := true; constant mreg : boolean := false; constant qreg : boolean := false; component fsm port ( clk : in std_logic; reset_n : in std_logic; en : in std_logic; rst : in std_logic; cnt_en : out std_logic; cnt_srst : out std_logic; memin_zero : out std_logic; we : out std_logic; hold_cntval : out std_logic; stateinfo : out std_logic_vector (2 downto 0); address : out std_logic_vector (9 downto 0)); end component; component countermem generic ( counterwidth : integer); port ( clk : in std_logic; cpuclk : in std_logic; reset_n : in std_logic; memin_zero : in std_logic; we : in std_logic; hold_cntval : in std_logic; address : in std_logic_vector(9 downto 0); fromcounter : in std_logic_vector(counterwidth-1 downto 0); cpuaddress : in std_logic_vector(9 downto 0); cpudata : out std_logic_vector(47 downto 0)); end component; component cnt576 generic ( Nbit : integer; shortpulse : boolean; areg : boolean; mreg : boolean; qreg : boolean); port ( clk : in std_logic; srst : in std_logic; glb_en : in std_logic; S : in std_logic_vector(575 downto 0); addr : in std_logic_vector(9 downto 0); q : out std_logic_vector(Nbit-1 downto 0)); end component; component ctrlregister port ( clk : in std_logic; cpuclk : in std_logic; reset_n : in std_logic; en : out std_logic; -- to fsm rst : out std_logic; -- to fsm stateinfo : in std_logic_vector(2 downto 0); -- from fsm soreor : in std_logic; -- from CB-B over SPA cpuaddress : out std_logic_vector(9 downto 0); -- to cmem cpudata : in std_logic_vector(47 downto 0); -- from cmem scsnaddress : in std_logic_vector(2 downto 0); -- from TL counter_IBO : in std_logic_vector(31 downto 0); -- from TL counter_OBI : out std_logic_vector(31 downto 0); -- to TL we : in std_logic; rd : in std_logic ); end component; signal en_i : std_logic; -- ctrl -> fsm signal rst_i : std_logic; -- ctrl -> fsm signal cpuaddress_i : std_logic_vector(9 downto 0); -- ctrl -> mem signal cpudata_i : std_logic_vector(47 downto 0); -- mem -> ctrl signal cnt_en_i : std_logic; -- fsm -> cnt signal cnt_srst_i : std_logic; -- fsm -> cnt signal memin_zero_i : std_logic; -- fsm -> mem signal we_i : std_logic; -- fsm -> mem signal hold_cntval_i : std_logic; -- fsm -> mem signal stateinfo_i : std_logic_vector (2 downto 0); -- fsm -> ctrl signal address_i : std_logic_vector (9 downto 0); -- fsm -> cnt,mem signal q_i : std_logic_vector(counterwidth-1 downto 0); -- cnt -> mem begin -- bev fsm_1 : fsm port map ( clk => clk, reset_n => reset_n, en => en_i, -- from ctrlregister rst => rst_i, -- from ctrlregister cnt_en => cnt_en_i, -- to cnt576 cnt_srst => cnt_srst_i, -- to cnt576 memin_zero => memin_zero_i, -- to countermem we => we_i, -- to countermem hold_cntval => hold_cntval_i, -- to countermem stateinfo => stateinfo_i, -- to ctrlregister address => address_i); -- to cnt576 and countermem countermem_1 : countermem generic map ( counterwidth => counterwidth) port map ( clk => clk, cpuclk => cpuclk, reset_n => reset_n, memin_zero => memin_zero_i, -- from fsm we => we_i, -- from fsm hold_cntval => hold_cntval_i, -- from fsm address => address_i, -- from fsm fromcounter => q_i, -- from cnt576 cpuaddress => cpuaddress_i, -- from ctrlregister cpudata => cpudata_i); -- to ctrlregister cnt576_1 : cnt576 generic map ( Nbit => counterwidth, shortpulse => false, areg => areg, mreg => mreg, qreg => qreg) port map ( clk => clk, srst => cnt_srst_i, glb_en => cnt_en_i, -- from fsm S => S, -- from TL addr => address_i, -- from fsm q => q_i); -- to countermem ctrlregister_1 : ctrlregister port map ( clk => clk, cpuclk => cpuclk, reset_n => reset_n, en => en_i, -- to fsm rst => rst_i, -- to fsm stateinfo => stateinfo_i, -- from fsm soreor => soreor, -- from TL from CB-B over SPA cpuaddress => cpuaddress_i, -- to countermem cpudata => cpudata_i, -- from countermem scsnaddress => address, -- from TL counter_IBO => counter_IBO, -- from TL counter_OBI => counter_OBI, -- from TL we => we, -- from TL rd => rd); -- from TL end bev;