library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity cnt576 is

  generic (
    Nbit       : integer := 16;
    shortpulse : boolean := false;
    areg       : boolean := false;
    mreg       : boolean := false;
    qreg       : boolean := false);

  port (
    clk    : in  std_logic;
    srst   : in  std_logic;
    glb_en : in  std_logic;
    S      : in  std_logic_vector(575 downto 0);
    addr   : in  std_logic_vector(9 downto 0);
    q      : out std_logic_vector(Nbit-1 downto 0));


end cnt576;

architecture behv of cnt576 is

  component top_counters
    generic (
      Na         : integer;
      Nm         : integer;
      Nbit       : integer;
      shortpulse : boolean;
      areg       : boolean;
      mreg       : boolean;
      qreg       : boolean
      );
    port (
      clk    : in  std_logic;
      srst   : in  std_logic;
      glb_en : in  std_logic;
      cntin  : in  std_logic_vector(2**Na-1 downto 0);
      raddr  : in  std_logic_vector(Na-1 downto 0);
      q      : out std_logic_vector(Nbit-1 downto 0));
  end component;

  constant Na     : integer := 6;
  constant Nm     : integer := 4;
  constant numblk : natural := 9;

  signal raddr_hi  : integer range 0 to numblk-1;
  signal raddr_hi2 : integer range 0 to numblk-1;
  signal raddr_lo  : std_logic_vector(Na-1 downto 0);

--  subtype caddr_t is std_logic_vector(Na-1 downto 0);
--  type addr_arr_t is array(0 to numblk-1) of caddr_t; 
--  signal addr_arr : addr_arr_t;

  subtype qblk_t is std_logic_vector(Nbit-1 downto 0);
  type qblk_arr_t is array(0 to numblk-1) of qblk_t;
  signal qblk_arr : qblk_arr_t;

begin  -- behv


  cnt_blktop : for i in 0 to numblk-1 generate
    top_counters_1 : top_counters
      generic map (
        Na         => Na,
        Nm         => Nm,
        Nbit       => Nbit,
        shortpulse => shortpulse,
        areg       => areg,
        mreg       => mreg,
        qreg       => qreg)
      port map (
        clk    => clk,
        srst   => srst,
        glb_en => glb_en,
        cntin  => S((i+1)*(2**Na)-1 downto i*(2**Na)),
        raddr  => raddr_lo,
        q      => qblk_arr(i));
  end generate cnt_blktop;

  -- split in hi and low address, register if areg true
  ra_reg : if areg generate
    process(clk)
    begin
      if rising_edge(clk) then
        raddr_hi <= conv_integer(addr(9 downto Na));
        raddr_lo <= addr(Na-1 downto 0);
      end if;
    end process;
  end generate;

  ra_dir : if not areg generate
    raddr_hi <= conv_integer(addr(9 downto Na));
    raddr_lo <= addr(Na-1 downto 0);
  end generate;

  -- register hi register if mreg true

  ra_mreg : if mreg generate
    process(clk)
    begin
      if rising_edge(clk) then
        raddr_hi2 <= raddr_hi;
      end if;
    end process;
  end generate;

  ra_mdir : if not mreg generate
    raddr_hi2 <= raddr_hi;
  end generate;

  -- addre

  -- q demultiplexer, register if qreg true

  q_reg : if qreg generate
    process(clk)
    begin
      if rising_edge(clk) then
        q <= qblk_arr(raddr_hi2);
      end if;
    end process;
  end generate;

  q_dir : if not qreg generate
    q <= qblk_arr(raddr_hi2);
  end generate;
  
end behv;