-- acnt: count 0..575 reports zero and wraps automatically. 9 downto 0 = 0..1023

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;

entity acnt is

  port (
    clk     : in  std_logic;
    reset_n : in  std_logic;
    acnt_clr: in  std_logic;
    acnt_en : in  std_logic;
    acnt_zero : out std_logic;
    address : out std_logic_vector (9 downto 0));

end acnt;

architecture behv of acnt is


  signal cntreg : std_logic_vector(9 downto 0);
  
begin  -- behv

  a_cnt_p: process (clk, reset_n)
  begin  -- process ws_cnt_p
    if reset_n = '0' then               -- asynchronous reset (active low)
      cntreg <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if acnt_clr = '1' then
        cntreg <= (others => '0');
      elsif acnt_en = '1' then
        if cntreg="1000111111" then
          cntreg <= (others => '0');
        else
          cntreg <= cntreg + 1; 
        end if;
      end if;
    end if;
  end process a_cnt_p;

  address <= cntreg;
  
  acnt_zero <= '1' when cntreg = (cntreg'high downto cntreg'low => '0') else '0';
  
end behv;