------------------------------------------------------------------------------- -- TLMU: top level Entity of TLMU FPGA ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; library UNISIM; use UNISIM.vcomponents.all; entity TLMU is generic ( version_id : std_logic_vector := x"00010001"; padCol : positive := 8; padRow : positive := 36); port ( -- Signals from DCS-A RESET_A : in std_logic; -- activ low (G17, in DS: SPARE1-A) CLK40_A : in std_logic; -- A20 SCSN_IN_A : in std_logic; -- C18 SCSN_OUT_A : out std_logic; -- C17 T_A : out std_logic_vector (7 downto 0); -- SPA_A : in std_logic; -- C15 SPB_A : in std_logic; -- F16 SPC_A : out std_logic; -- F20 SPD_A : out std_logic; -- G15 EN_A : in std_logic; -- C19 -- Signals from DCS-B RESET_B : in std_logic; -- activ low (AH17, in DS:SPARE1-B) CLK40_B : in std_logic; -- AN14 SCSN_IN_B : in std_logic; -- AP14 SCSN_OUT_B : out std_logic; -- AK17 T_B : out std_logic_vector (7 downto 0); -- SPA_B : in std_logic; -- AP24 SPB_B : in std_logic; -- AM23 SPC_B : out std_logic; -- AN23 SPD_B : out std_logic; -- AN22 EN_B : in std_logic; -- AJ15 -- common I/O) LED : out std_logic_vector (8 downto 1); SA : in std_logic_vector(padCol*padRow-1 downto 0); SB : in std_logic_vector(padCol*padRow-1 downto 0); -- Temperature Sensor U2 (SHT11) T_Data : inout std_logic; T_Clk : out std_logic ); end TLMU; ------------------------------------------------------------------------------- -- ARCHITECTURE ------------------------------------------------------------------------------- architecture behv of TLMU is constant OutClockMultiplier : integer := 4; constant OutClockDivisor : integer := 1; constant Oserdes_factor : integer := 4; ------------------------------------------------------------------------------- -- COMPONENTS ------------------------------------------------------------------------------- component AB_switch port ( AB_OBI : out std_logic_vector(31 downto 0); clocksel : out std_logic; RESET_A : in std_logic; SCSN_IN_A : in std_logic; SCSN_OUT_A : out std_logic; T_A : out std_logic_vector (7 downto 0); SPA_A : in std_logic; SPB_A : in std_logic; SPC_A : out std_logic; SPD_A : out std_logic; EN_A : in std_logic; RESET_B : in std_logic; SCSN_IN_B : in std_logic; SCSN_OUT_B : out std_logic; T_B : out std_logic_vector (7 downto 0); SPA_B : in std_logic; SPB_B : in std_logic; SPC_B : out std_logic; SPD_B : out std_logic; EN_B : in std_logic; locked : in std_logic; RESET : out std_logic; SCSN_IN : out std_logic; SCSN_OUT : in std_logic; T : in std_logic_vector (7 downto 0); SPA : out std_logic; SPB : out std_logic; SPC : in std_logic; SPD : in std_logic); end component; -- component TLMU_clk port ( I_A : in std_logic; I_B : in std_logic; clocksel : in std_logic; O40 : out std_logic; O160 : out std_logic; O120 : out std_logic; locked : out std_logic; OCLKTA : out std_logic); end component; -- component mcm_network_interface port ( ser0_din : in std_logic; ser0_dout : out std_logic; ser1_din : in std_logic; ser1_dout : out std_logic; bus_addr : out std_logic_vector(15 downto 0); bus_dout : out std_logic_vector(31 downto 0); bus_din : in std_logic_vector(31 downto 0); bus_req : out std_logic; bus_we : out std_logic; bus_ack : in std_logic; chipRST_n : out std_logic; reset_n : in std_logic; clk_buf_disable : out std_logic; clk_buf : in std_logic; clk : in std_logic); end component; -- component adremux port ( bus_addr : in std_logic_vector(15 downto 0); bus_din : out std_logic_vector(31 downto 0); bus_we : in std_logic; bus_req : in std_logic; id_register_OBI : in std_logic_vector(31 downto 0); led_register_OBI : in std_logic_vector(31 downto 0); AB_OBI : in std_logic_vector(31 downto 0); counter_OBI : in std_logic_vector(31 downto 0); mask_OBI : in std_logic_vector(31 downto 0); coinc_matrix0_OBI : in std_logic_vector(31 downto 0); coinc_matrix1_OBI : in std_logic_vector(31 downto 0); coinc_matrix2_OBI : in std_logic_vector(31 downto 0); ccnt0_OBI : in std_logic_vector(31 downto 0); ccnt1_OBI : in std_logic_vector(31 downto 0); ccnt2_OBI : in std_logic_vector(31 downto 0); TA_OBI : in std_logic_vector(31 downto 0); multi_OBI : in std_logic_vector(31 downto 0); trigger_input_stretch_OBI : in std_logic_vector(31 downto 0); tseq_OBI : in std_logic_vector(31 downto 0); oswitch_OBI : in std_logic_vector(31 downto 0); secnt_OBI : in std_logic_vector(31 downto 0); tsens_OBI : in std_logic_vector(31 downto 0); tlmusend_OBI : in std_logic_vector(31 downto 0); led_register_we : out std_logic; count_we : out std_logic; count_rd : out std_logic; mask_we : out std_logic; coinc_matrix0_we : out std_logic; coinc_matrix1_we : out std_logic; coinc_matrix2_we : out std_logic; ccnt0_we : out std_logic; ccnt1_we : out std_logic; ccnt2_we : out std_logic; TA_we : out std_logic; multi_we : out std_logic; trigger_input_stretch_we : out std_logic; tseq_we : out std_logic; oswitch_we : out std_logic; secnt_we : out std_logic; tsens_we : out std_logic; tlmusend_we : out std_logic); end component; -- component id_register generic ( version_id : std_logic_vector); port ( address : in std_logic; data : out std_logic_vector(31 downto 0)); end component; -- component ledregister port ( clk : in std_logic; reset_n : in std_logic; we : in std_logic; led_register_IBO : in std_logic_vector(31 downto 0); led_register_OBI : out std_logic_vector(31 downto 0); led_debug_in_A : in std_logic_vector(7 downto 0); led : out std_logic_vector(7 downto 0)); end component; -- component trigger_input_sort port ( S_first_all_A_then_all_C : in std_logic_vector(575 downto 0); S_SM_by_SM : out std_logic_vector(575 downto 0)); end component; -- component trigger_input_filter generic ( use_sfr : boolean; use_asy : boolean; oreg : boolean); port ( reset_n : in std_logic; clk120 : in std_logic; clk40 : in std_logic; Sa : in std_logic_vector(575 downto 0); Ss : out std_logic_vector(575 downto 0)); end component; -- component trigger_input_stage port ( reset_n : in std_logic; clk : in std_logic; Sa : in std_logic_vector(2*padCol*padRow-1 downto 0); Ss : out std_logic_vector(2*padCol*padRow-1 downto 0)); end component; -- component trigger_input_stretch port ( clk40 : in std_logic; clkcpu : in std_logic; reset_n : in std_logic; we : in std_logic; address : in std_logic_vector(1 downto 0); trigger_input_stretch_IBO : in std_logic_vector(31 downto 0); trigger_input_stretch_OBI : out std_logic_vector(31 downto 0); Sshort : in std_logic_vector(575 downto 0); Slong : out std_logic_vector(575 downto 0); coinc_in : in std_logic_vector(2 downto 0); coinc_out : out std_logic_vector(2 downto 0)); end component; -- component trigger_input_mask generic ( width : integer); port ( reset_n : in std_logic; clk : in std_logic; S_in : in std_logic_vector(width-1 downto 0); S_out : out std_logic_vector(width-1 downto 0); imask : out std_logic_vector(width-1 downto 0); we : in std_logic; address : in std_logic_vector(4 downto 0); mask_IBO : in std_logic_vector(31 downto 0); mask_OBI : out std_logic_vector(31 downto 0)); end component; -- component coinc_matrix generic ( width : integer); port ( reset_n : in std_logic; clk : in std_logic; S_in : in std_logic_vector(width-1 downto 0); trigger : out std_logic; we : in std_logic; address : in std_logic_vector(9 downto 0); coinc_matrix_IBO : in std_logic_vector(31 downto 0); coinc_matrix_OBI : out std_logic_vector(31 downto 0)); end component; -- component coinc_counter generic ( use_asy : boolean); port ( cntclk : in std_logic; cpuclk : in std_logic; reset_n : in std_logic; soreor : in std_logic; we : in std_logic; address : in std_logic_vector(2 downto 0); ccnt_IBO : in std_logic_vector(31 downto 0); ccnt_OBI : out std_logic_vector(31 downto 0); T : in std_logic); end component; -- component coinc_hg generic ( width : integer); port ( reset_n : in std_logic; clk : in std_logic; S_in : in std_logic_vector(width-1 downto 0); trigger : out std_logic_vector(3 downto 0); we : in std_logic; address : in std_logic_vector(9 downto 0); coinc_hg_IBO : in std_logic_vector(31 downto 0); coinc_hg_OBI : out std_logic_vector(31 downto 0)); end component; -- component cnt576x48 port ( clk : in std_logic; cpuclk : in std_logic; reset_n : in std_logic; S : in std_logic_vector(575 downto 0); soreor : in std_logic; we : in std_logic; rd : in std_logic; address : in std_logic_vector(2 downto 0); counter_IBO : in std_logic_vector(31 downto 0); counter_OBI : out std_logic_vector(31 downto 0)); end component; -- component TA port ( taclk : in std_logic; scsnclk : in std_logic; reset_n : in std_logic; address : in std_logic_vector(13 downto 0); we : in std_logic; TA_OBI : out std_logic_vector(31 downto 0); TA_IBO : in std_logic_vector(31 downto 0); S : in std_logic_vector(575 downto 0); T : in std_logic_vector(31 downto 0)); end component; -- component multi_top port ( clk : in std_logic; cpuclk : in std_logic; cntclk : in std_logic; reset_n : in std_logic; S : in std_logic_vector(575 downto 0); T : out std_logic_vector(8 downto 0); soreor : in std_logic; we : in std_logic; address : in std_logic_vector(5 downto 0); multi_IBO : in std_logic_vector(31 downto 0); multi_OBI : out std_logic_vector(31 downto 0)); end component; -- component trigger_sequencer port ( clk40 : in std_logic; cpuclk : in std_logic; reset_n : in std_logic; tseq_IBO : in std_logic_vector(31 downto 0); tseq_OBI : out std_logic_vector(31 downto 0); we : in std_logic; address : in std_logic_vector(9 downto 0); Tout : out std_logic_vector(4 downto 0)); end component; -- component output_switch port ( cpuclk : in std_logic; clk40 : in std_logic; reset_n : in std_logic; oswitch_IBO : in std_logic_vector(31 downto 0); oswitch_OBI : out std_logic_vector(31 downto 0); we : in std_logic; address : in std_logic_vector(3 downto 0); Tout : out std_logic_vector(7 downto 0); Tin : in std_logic_vector(31 downto 0)); end component; -- component soreorcnt port ( cntclk : in std_logic; cpuclk : in std_logic; reset_n : in std_logic; soreor : in std_logic; address : in std_logic_vector(1 downto 0); we : in std_logic; cntout : out std_logic_vector(47 downto 0); secnt_IBO : in std_logic_vector(31 downto 0); secnt_OBI : out std_logic_vector(31 downto 0)); end component; -- component tsens port ( clk : in std_logic; reset_n : in std_logic; we : in std_logic; tsens_IBO : in std_logic_vector(31 downto 0); tsens_OBI : out std_logic_vector(31 downto 0); T_Data : inout std_logic; T_Clk : out std_logic); end component; -- component tlmusend generic ( OutClockMultiplier : integer; OutClockDivisor : integer; Oserdes_factor : integer; serw : integer); port ( clk40 : in std_logic; reset_n : in std_logic; Tin : in std_logic_vector(31 downto 0); Tout : out std_logic_vector(serw-1 downto 0); senddata : in std_logic_vector(575 downto 0); simdata : in std_logic_vector(575 downto 0); time_counter : in std_logic_vector(47 downto 0); start : in std_logic; active : out std_logic; address : in std_logic_vector(3 downto 0); we : in std_logic; tlmusend_IBO : in std_logic_vector(31 downto 0); tlmusend_OBI : out std_logic_vector(31 downto 0)); end component; ------------------------------------------------------------------------------- -- SIGNALS ------------------------------------------------------------------------------- signal led_i : std_logic_vector(7 downto 0); signal reset_n : std_logic; -- Signals to/from DCS Board A or B (AB_switch) signal clocksel : std_logic; -- 0 : clock from A, 1: clock from B signal RESET : std_logic; signal SCSN_IN : std_logic; signal SCSN_OUT : std_logic; signal T : std_logic_vector (7 downto 0); signal SPA : std_logic; signal SPB : std_logic; signal SPC : std_logic; signal SPD : std_logic; signal EN : std_logic; -- Clocks (TLMU_clk) signal clk40 : std_logic; signal clk160 : std_logic; signal clk120 : std_logic; signal clkta : std_logic; signal clkscsn : std_logic; -- SCSN interface signals (mcm_network_interface) signal bus_addr : std_logic_vector(15 downto 0); signal bus_dout : std_logic_vector(31 downto 0); signal bus_din : std_logic_vector(31 downto 0); signal bus_req : std_logic; signal bus_we : std_logic; signal scsn_reset_i : std_logic; -- Data Signals to BUS (xxx_register_OBI= xxx-Out Bus In) signal id_register_OBI : std_logic_vector(31 downto 0); signal led_register_OBI : std_logic_vector(31 downto 0); signal AB_OBI : std_logic_vector(31 downto 0); signal counter_OBI : std_logic_vector(31 downto 0); signal mask_OBI : std_logic_vector(31 downto 0); signal coinc_matrix0_OBI : std_logic_vector(31 downto 0); signal coinc_matrix1_OBI : std_logic_vector(31 downto 0); signal coinc_matrix2_OBI : std_logic_vector(31 downto 0); signal ccnt0_OBI : std_logic_vector(31 downto 0); signal ccnt1_OBI : std_logic_vector(31 downto 0); signal ccnt2_OBI : std_logic_vector(31 downto 0); signal coinc_hg_OBI : std_logic_vector(31 downto 0); signal TA_OBI : std_logic_vector(31 downto 0); signal multi_OBI : std_logic_vector(31 downto 0); signal trigger_input_stretch_OBI : std_logic_vector(31 downto 0); signal tseq_OBI : std_logic_vector(31 downto 0); signal oswitch_OBI : std_logic_vector(31 downto 0); signal secnt_OBI : std_logic_vector(31 downto 0); signal tsens_OBI : std_logic_vector(31 downto 0); signal tlmusend_OBI : std_logic_vector(31 downto 0); -- Write enable signals signal led_register_we : std_logic; signal count_we : std_logic; signal mask_we : std_logic; signal coinc_matrix0_we : std_logic; signal coinc_matrix1_we : std_logic; signal coinc_matrix2_we : std_logic; signal ccnt0_we : std_logic; signal ccnt1_we : std_logic; signal ccnt2_we : std_logic; signal TA_we : std_logic; signal multi_we : std_logic; signal trigger_input_stretch_we : std_logic; signal tseq_we : std_logic; signal oswitch_we : std_logic; signal secnt_we : std_logic; signal tsens_we : std_logic; signal tlmusend_we : std_logic; -- Read request signals signal count_rd : std_logic; -- Filtered iin input_stage: Input SA,SB signal Sin : std_logic_vector(2*padCol*padRow-1 downto 0); signal Sasync : std_logic_vector(2*padCol*padRow-1 downto 0); signal Smasked : std_logic_vector(2*padCol*padRow-1 downto 0); signal Ssynced120 : std_logic_vector(2*padCol*padRow-1 downto 0); signal Ssynced40 : std_logic_vector(2*padCol*padRow-1 downto 0); signal SsyncedTA : std_logic_vector(2*padCol*padRow-1 downto 0); signal Sstretched40 : std_logic_vector(2*padCol*padRow-1 downto 0); -- Contents of Mask register, to be passed to tlmusend signal imask_i : std_logic_vector(2*padCol*padRow-1 downto 0); -- Signal to be reduced by configuration signal Tfrom_matrix_to_reducer : std_logic_vector(2 downto 0); -- SOR/EOR from DCS Board routed through CB-B (1 after SOR, 0 after EOR) signal soreor : std_logic; -- SOREOR counter ro be passed to tlmusend signal cntout_i : std_logic_vector(47 downto 0); -- testsignal for TA signal tv : std_logic_vector(15 downto 0); -------- input signals to Trigger Output Switch -- Signal from 3 Coinc matrixes 0 to output switch signal Tcoinc : std_logic_vector(2 downto 0); -- Coincidence High Granularity signal Tcoinc_hg : std_logic_vector(3 downto 0); -- Signal from 9 Multiplicity Classes to output switch signal Tmult : std_logic_vector(8 downto 0); -- Output Signal from Trigger Sequencer signal Tsequencer : std_logic_vector(4 downto 0); -- Tin_i: combined Signal to output switch signal Tin_i : std_logic_vector(31 downto 0); -- Tsend from tlmusend to output switch signal Tsend : std_logic_vector(7 downto 0); -- debugging signal locked : std_logic; ------------------------------------------------------------------------------- -- BEGIN ARCHITECTURE ------------------------------------------------------------------------------- begin -- behv AB_switch_1 : AB_switch port map ( AB_OBI => AB_OBI, clocksel => clocksel, RESET_A => RESET_A, SCSN_IN_A => SCSN_IN_A, SCSN_OUT_A => SCSN_OUT_A, T_A => T_A, SPA_A => SPA_A, SPB_A => SPB_A, SPC_A => SPC_A, SPD_A => SPD_A, EN_A => EN_A, RESET_B => RESET_B, SCSN_IN_B => SCSN_IN_B, SCSN_OUT_B => SCSN_OUT_B, T_B => T_B, SPA_B => SPA_B, SPB_B => SPB_B, SPC_B => SPC_B, SPD_B => SPD_B, EN_B => EN_B, locked => locked, RESET => RESET, SCSN_IN => SCSN_IN, SCSN_OUT => SCSN_OUT, T => T, SPA => SPA, SPB => SPB, SPC => SPC, SPD => SPD); -- reset_n <= not RESET; soreor <= SPA; ------------------------------------------------------------------------------- TLMU_clk_1 : TLMU_clk port map ( I_A => CLK40_B, I_B => CLK40_A, clocksel => not clocksel, -- I_A => CLK40_A, -- I_B => CLK40_B, -- clocksel => clocksel, O40 => clk40, O160 => clk160, O120 => clk120, locked => locked, OCLKTA => clkta); clkscsn <= clk40; ------------------------------------------------------------------------------- mcm_network_interface_1 : mcm_network_interface port map ( ser0_din => SCSN_IN, ser0_dout => SCSN_OUT, ser1_din => '0', ser1_dout => open, bus_addr => bus_addr, bus_dout => bus_dout, bus_din => bus_din, bus_req => bus_req, bus_we => bus_we, bus_ack => '1', chipRST_n => scsn_reset_i, reset_n => reset_n, clk_buf_disable => open, clk_buf => clkscsn, clk => clkscsn); ------------------------------------------------------------------------------- adremux_1 : adremux port map ( bus_addr => bus_addr, bus_din => bus_din, bus_we => bus_we, bus_req => bus_req, id_register_OBI => id_register_OBI, led_register_OBI => led_register_OBI, AB_OBI => AB_OBI, counter_OBI => counter_OBI, mask_OBI => mask_OBI, coinc_matrix0_OBI => coinc_matrix0_OBI, coinc_matrix1_OBI => coinc_matrix1_OBI, coinc_matrix2_OBI => coinc_matrix2_OBI, ccnt0_OBI => ccnt0_OBI, ccnt1_OBI => ccnt1_OBI, ccnt2_OBI => ccnt2_OBI, TA_OBI => TA_OBI, multi_OBI => multi_OBI, trigger_input_stretch_OBI => trigger_input_stretch_OBI, tseq_OBI => tseq_OBI, oswitch_OBI => oswitch_OBI, secnt_OBI => secnt_OBI, tsens_OBI => tsens_OBI, tlmusend_OBI => tlmusend_OBI, led_register_we => led_register_we, count_we => count_we, count_rd => count_rd, mask_we => mask_we, coinc_matrix0_we => coinc_matrix0_we, coinc_matrix1_we => coinc_matrix1_we, coinc_matrix2_we => coinc_matrix2_we, ccnt0_we => ccnt0_we, ccnt1_we => ccnt1_we, ccnt2_we => ccnt2_we, TA_we => TA_we, multi_we => multi_we, trigger_input_stretch_we => trigger_input_stretch_we, tseq_we => tseq_we, oswitch_we => oswitch_we, secnt_we => secnt_we, tsens_we => tsens_we, tlmusend_we => tlmusend_we); ------------------------------------------------------------------------------- id_register_1 : id_register generic map ( version_id => version_id) port map ( address => bus_addr(0), data => id_register_OBI); ------------------------------------------------------------------------------- ledregister_1 : ledregister port map ( clk => clkscsn, reset_n => reset_n, we => led_register_we, led_register_IBO => bus_dout, led_register_OBI => led_register_OBI, led_debug_in_A => "10101010", led => LED(8 downto 1)); ------------------------------------------------------------------------------- Sin <= SB & SA; trigger_input_sort_1 : trigger_input_sort port map ( S_first_all_A_then_all_C => Sin, S_SM_by_SM => Sasync); trigger_input_filter_1 : trigger_input_filter generic map ( use_sfr => false, use_asy => true, oreg => true) port map ( reset_n => reset_n, clk120 => clk120, clk40 => clk40, Sa => Sasync, Ss => Ssynced40); trigger_input_stage_1 : trigger_input_stage port map ( reset_n => reset_n, clk => clkscsn, Sa => Sasync, Ss => Ssynced120); trigger_input_stage_3 : trigger_input_stage port map ( reset_n => reset_n, clk => clkta, Sa => Sasync, Ss => SsyncedTA); ------------------------------------------------------------------------------- trigger_input_stretch_1 : trigger_input_stretch port map ( clk40 => clk40, clkcpu => clkscsn, reset_n => reset_n, we => trigger_input_stretch_we, address => bus_addr(1 downto 0), trigger_input_stretch_IBO => bus_dout, trigger_input_stretch_OBI => trigger_input_stretch_OBI, Sshort => Smasked, Slong => Sstretched40, coinc_in => Tfrom_matrix_to_reducer, coinc_out => Tcoinc); ------------------------------------------------------------------------------- trigger_input_mask_1 : trigger_input_mask generic map ( width => 2*padCol*padRow) port map ( reset_n => reset_n, clk => clkscsn, S_in => Ssynced40, S_out => Smasked, imask => imask_i, we => mask_we, address => bus_addr(4 downto 0), mask_IBO => bus_dout, mask_OBI => mask_OBI); ------------------------------------------------------------------------------- coinc_matrix_0 : coinc_matrix generic map ( width => 2*padCol*padRow) port map ( reset_n => reset_n, clk => clkscsn, S_in => Sstretched40, trigger => Tfrom_matrix_to_reducer(0), we => coinc_matrix0_we, address => bus_addr(9 downto 0), coinc_matrix_IBO => bus_dout, coinc_matrix_OBI => coinc_matrix0_OBI); coinc_matrix_1 : coinc_matrix generic map ( width => 2*padCol*padRow) port map ( reset_n => reset_n, clk => clkscsn, S_in => Sstretched40, trigger => Tfrom_matrix_to_reducer(1), we => coinc_matrix1_we, address => bus_addr(9 downto 0), coinc_matrix_IBO => bus_dout, coinc_matrix_OBI => coinc_matrix1_OBI); coinc_matrix_2 : coinc_matrix generic map ( width => 2*padCol*padRow) port map ( reset_n => reset_n, clk => clkscsn, S_in => Sstretched40, trigger => Tfrom_matrix_to_reducer(2), we => coinc_matrix2_we, address => bus_addr(9 downto 0), coinc_matrix_IBO => bus_dout, coinc_matrix_OBI => coinc_matrix2_OBI); ------------------------------------------------------------------------------- ccnt_0 : coinc_counter generic map ( use_asy => true) port map ( cntclk => clk40, cpuclk => clkscsn, reset_n => reset_n, soreor => soreor, we => ccnt0_we, address => bus_addr(2 downto 0), ccnt_IBO => bus_dout, ccnt_OBI => ccnt0_OBI, T => T(0)); ccnt_1 : coinc_counter generic map ( use_asy => true) port map ( cntclk => clk40, cpuclk => clkscsn, reset_n => reset_n, soreor => soreor, we => ccnt1_we, address => bus_addr(2 downto 0), ccnt_IBO => bus_dout, ccnt_OBI => ccnt1_OBI, T => T(1)); ccnt_2 : coinc_counter generic map ( use_asy => true) port map ( cntclk => clk40, cpuclk => clkscsn, reset_n => reset_n, soreor => soreor, we => ccnt2_we, address => bus_addr(2 downto 0), ccnt_IBO => bus_dout, ccnt_OBI => ccnt2_OBI, T => T(2)); ------------------------------------------------------------------------------- coinc_hg_1: coinc_hg generic map ( width => 576) port map ( reset_n => reset_n, clk => clk40, S_in => Sstretched40, trigger => Tcoinc_hg, we => '0', address => bus_addr(9 downto 0), coinc_hg_IBO => bus_dout, coinc_hg_OBI => coinc_hg_OBI); ------------------------------------------------------------------------------- cnt576x48_1 : cnt576x48 port map ( clk => clk40, cpuclk => clkscsn, reset_n => reset_n, S => Ssynced40, soreor => soreor, we => count_we, rd => count_rd, address => bus_addr(2 downto 0), counter_IBO => bus_dout, counter_OBI => counter_OBI); ------------------------------------------------------------------------------- testsignal : process (clk40, reset_n) begin -- process testsignal if reset_n = '0' then -- asynchronous reset (active low) tv <= (others => '0'); elsif clkta'event and clkta = '1' then -- rising clock edge tv <= tv + 1; end if; end process testsignal; ------------------------------------------------------------------------------- TA_1 : TA port map ( taclk => clkta, scsnclk => clkscsn, reset_n => reset_n, address => bus_addr(13 downto 0), we => TA_we, TA_OBI => TA_OBI, TA_IBO => bus_dout, S => SsyncedTA, T(31 downto 28) => Ssynced40(299 downto 296), T(27 downto 24) => Ssynced40(3 downto 0), T(23 downto 20) => Sstretched40(299 downto 296), T(19 downto 16) => Sstretched40(3 downto 0), T(15) => SCSN_OUT, T(14) => SCSN_IN, T(13) => led_register_we, T(12) => clk40, T(11 downto 9) => tv(2 downto 0), T(8) => SPB, T(7 downto 0) => T); ------------------------------------------------------------------------------- multi_top_1 : multi_top port map ( clk => clk120, cpuclk => clkscsn, cntclk => clk40, reset_n => reset_n, S => Smasked, T => Tmult, soreor => soreor, we => multi_we, address => bus_addr(5 downto 0), multi_IBO => bus_dout, multi_OBI => multi_OBI); ------------------------------------------------------------------------------- trigger_sequencer_1 : trigger_sequencer port map ( clk40 => clk40, cpuclk => clkscsn, reset_n => reset_n, tseq_IBO => bus_dout, tseq_OBI => tseq_OBI, we => tseq_we, address => bus_addr(9 downto 0), Tout => Tsequencer); ------------------------------------------------------------------------------- -- Tin(2 downto 0) => Tcoinc, -- default on Tout(2..0) -- Tin(11 downto 3) => Tmult, -- default on Tout(7..3), (11..3 unmapped) -- Tin(16 downto 12) => Tsequencer, -- default unmapped -- Tin(31 downto 17) => "000000000000000"); -- Tin_i <= (31 downto 25 => '0') & Tsend & Tsequencer & Tmult & Tcoinc; -- Tin_i <= (31 downto 17 => '0') & Tsequencer & Tmult & Tcoinc; Tin_i <= (31 downto 18 => '0') & Tcoinc_hg(0) & Tsequencer & Tmult & Tcoinc; output_switch_1 : output_switch port map ( cpuclk => clkscsn, clk40 => clk40, reset_n => reset_n, oswitch_IBO => bus_dout, oswitch_OBI => oswitch_OBI, we => oswitch_we, address => bus_addr(3 downto 0), Tout => T, -- to output and TA Tin => Tin_i); ------------------------------------------------------------------------------- soreorcnt_1 : soreorcnt port map ( cntclk => clk40, cpuclk => clkscsn, reset_n => reset_n, soreor => soreor, address => bus_addr(1 downto 0), we => secnt_we, cntout => cntout_i, secnt_IBO => bus_dout, secnt_OBI => secnt_OBI); ------------------------------------------------------------------------------- tsens_1 : tsens port map ( clk => clkscsn, reset_n => reset_n, we => tsens_we, tsens_IBO => bus_dout, tsens_OBI => tsens_OBI, T_Data => T_Data, T_Clk => T_Clk); ------------------------------------------------------------------------------- tlmusend_1 : tlmusend generic map ( OutClockMultiplier => OutClockMultiplier, OutClockDivisor => OutClockDivisor, Oserdes_factor => Oserdes_factor, serw => 8) port map ( clk40 => clk40, reset_n => reset_n, Tin => Tin_i, Tout => Tsend, senddata => Ssynced40, simdata => imask_i, time_counter => cntout_i, start => '0', active => open, address => bus_addr(3 downto 0), we => tlmusend_we, tlmusend_IBO => bus_dout, tlmusend_OBI => tlmusend_OBI); --T_A <= Tsend; end behv;