-- ta_acnt: count 0..511 reports acnt_eq, when address==stopadd

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity ta_acnt is

  port (
    clk      : in  std_logic;
    reset_n  : in  std_logic;
    acnt_clr : in  std_logic;
    acnt_en  : in  std_logic;
    acnt_sa  : out std_logic;
    stopadd  : in  std_logic_vector(8 downto 0);
    acnt_ps  : out std_logic;
    presadd  : in  std_logic_vector(8 downto 0);
    address  : out std_logic_vector (8 downto 0));

end ta_acnt;

architecture behv of ta_acnt is


  signal cntreg : std_logic_vector(8 downto 0);
  
begin  -- behv

  a_cnt_p : process (clk, reset_n)
  begin  -- process ws_cnt_p
    if reset_n = '0' then               -- asynchronous reset (active low)
      cntreg <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if acnt_clr = '1' then
        cntreg <= (others => '0');
      elsif acnt_en = '1' then
        if cntreg = "111111111" then
          cntreg <= (others => '0');
        else
          cntreg <= cntreg + 1;
        end if;
      end if;
    end if;
  end process a_cnt_p;

  address <= cntreg;

  acnt_sa <= '1' when cntreg = stopadd else '0';
  acnt_ps <= '1' when cntreg = presadd else '0';  
  
end behv;