-------------------------------------------------------------------------------
-- Title      : Testbench for design "waitstate"
-- Project    : 
-------------------------------------------------------------------------------
-- File       : waitstate_tb.vhd
-- Author     : tkrawuts
-- Company    : 
-- Created    : 2009-07-03
-- Last update: 2009-07-03
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2009 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2009-07-03  1.0      tkrawuts	Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------------------------------------

entity waitstate_tb is

end waitstate_tb;

-------------------------------------------------------------------------------

architecture dut of waitstate_tb is

  component waitstate
    generic (
      cntwidth : integer);
    port (
      clk     : in  std_logic;
      reset_n : in  std_logic;
      val     : in  std_logic_vector(cntwidth-1 downto 0);
      start   : in  std_logic;
      expired : out std_logic);
  end component;

  -- component generics
  constant cntwidth : integer := 3;

  -- component ports
  signal clk     : std_logic;
  signal reset_n : std_logic;
  signal val     : std_logic_vector(cntwidth-1 downto 0);
  signal start   : std_logic;
  signal expired : std_logic;

  -- clock
  signal Clki : std_logic := '1';


  constant period : time := 10 ns;
  constant halfperiod : time := period/2;
  
begin  -- dut

  -- component instantiation
  DUT: waitstate
    generic map (
      cntwidth => cntwidth)
    port map (
      clk     => Clki,
      reset_n => reset_n,
      val     => val,
      start   => start,
      expired => expired);

  -- clock generation
  Clki <= not Clki after halfperiod;

  -- waveform generation
  WaveGen_Proc: process
  begin
    -- insert signal assignments here
    reset_n <= '1'; val <= "000" ; start <= '0';
    wait for period;
    reset_n <= '0'; val <= "000" ; start <= '0';
    wait for 3*period;
    reset_n <= '1'; val <= "000" ; start <= '0';
    wait for 6*period;

    -- now 10*period, start

    val <= "001" ; start <= '1';
    wait for 1*period;
    val <= "000" ; start <= '0';
    wait for 9*period;

    
    val <= "010" ; start <= '1';
    wait for 2*period;
    val <= "000" ; start <= '0';
    wait for 8*period;

    val <= "011" ; start <= '1';
    wait for 3*period;
    val <= "000" ; start <= '0';
    wait for 7*period;

    val <= "100" ; start <= '1';
    wait for 4*period;
    val <= "000" ; start <= '0';
    wait for 6*period;
    
    val <= "101" ; start <= '1';
    wait for 5*period;
    val <= "000" ; start <= '0';
    wait for 5*period;

    val <= "110" ; start <= '1';
    wait for 6*period;
    val <= "000" ; start <= '0';
    wait for 4*period;

    val <= "111" ; start <= '1';
    wait for 7*period;
    val <= "000" ; start <= '0';
    wait for 13*period;

    val <= "001" ; start <= '0';
    wait for 12*period;
    val <= "100" ; start <= '1';
    wait for 4*period;
    val <= "000" ; start <= '0';
    wait for 8*period;
    


        wait;
  end process WaveGen_Proc;

  

end dut;

-------------------------------------------------------------------------------

configuration waitstate_tb_dut_cfg of waitstate_tb is
  for dut
  end for;
end waitstate_tb_dut_cfg;

-------------------------------------------------------------------------------