------------------------------------------------------------------------------- -- Title : Testbench for design "trigger_sequencer" -- Project : ------------------------------------------------------------------------------- -- File : trigger_sequencer_tb.vhd -- Author : U-KRAW\tkrawuts -- Company : -- Created : 2009-10-25 -- Last update: 2009-11-02 -- Platform : -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2009 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2009-10-25 1.0 tkrawuts Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- entity trigger_sequencer_tb is end trigger_sequencer_tb; ------------------------------------------------------------------------------- architecture dut of trigger_sequencer_tb is component trigger_sequencer port ( clk40 : in std_logic; cpuclk : in std_logic; reset_n : in std_logic; tseq_IBO : in std_logic_vector(31 downto 0); tseq_OBI : out std_logic_vector(31 downto 0); we : in std_logic; address : in std_logic_vector(9 downto 0); Tout : out std_logic_vector(4 downto 0)); end component; -- component ports signal clk40 : std_logic; signal cpuclk : std_logic; signal reset_n : std_logic; signal tseq_IBO : std_logic_vector(31 downto 0); signal tseq_OBI : std_logic_vector(31 downto 0); signal we : std_logic; signal address : std_logic_vector(9 downto 0); signal Tout : std_logic_vector(4 downto 0); -- clock -- signal Clk : std_logic := '1'; signal Clki : std_logic := '1'; signal CpuClki : std_logic := '1'; constant period : time := 25 ns; constant halfperiod : time := period/2; constant cpuperiod : time := period/3; constant halfcpuperiod : time := cpuperiod/2; begin -- dut -- component instantiation DUT: trigger_sequencer port map ( clk40 => Clki, cpuclk => CpuClki, reset_n => reset_n, tseq_IBO => tseq_IBO, tseq_OBI => tseq_OBI, we => we, address => address, Tout => Tout); -- clock generation Clki <= not Clki after halfperiod; CpuClki <= not CpuClki after halfcpuperiod; -- waveform generation WaveGen_Proc: process begin -- insert signal assignments here reset_n <= '1'; tseq_IBO <= x"00000000" ; we <= '0'; address <= "00" & x"00" ; wait for period; reset_n <= '0'; wait for 3*period; reset_n <= '1'; wait for 6*period; -- Write to seq mem report "Write to mem" severity note; address <= "10" & x"00" ; tseq_IBO <= "00" & x"000020" & '0' & "00001"; we <= '1'; wait for cpuperiod; address <= "00" & x"00" ; tseq_IBO <= x"0000000" & "0000"; we <= '0'; wait for cpuperiod; report "Write to mem" severity note; address <= "10" & x"01" ; tseq_IBO <= "00" & x"000000" & '0' & "00001"; we <= '1'; wait for cpuperiod; address <= "00" & x"00" ; tseq_IBO <= x"00000000" ; we <= '0'; wait for cpuperiod; report "Write to mem" severity note; address <= "10" & x"02" ; tseq_IBO <= "00" & x"000000" & '0' & "00001"; we <= '1'; wait for cpuperiod; address <= "00" & x"00" ; tseq_IBO <= x"0000000" & "0000"; we <= '0'; wait for cpuperiod; report "Write to mem" severity note; address <= "10" & x"03" ; tseq_IBO <= "00" & x"000002" & '0' & "00001"; we <= '1'; wait for cpuperiod; address <= "00" & x"00" ; tseq_IBO <= x"0000000" & "0000"; we <= '0'; wait for cpuperiod; report "Write to mem" severity note; address <= "10" & x"04" ; tseq_IBO <= "00" & x"000005" & '0' & "00001"; we <= '1'; wait for cpuperiod; address <= "00" & x"00" ; tseq_IBO <= x"0000000" & "0000"; we <= '0'; wait for cpuperiod; report "Write to mem last pattern" severity note; address <= "10" & x"05" ; tseq_IBO <= "00" & x"000000" & '1' & "00001"; we <= '1'; wait for cpuperiod; address <= "00" & x"00" ; tseq_IBO <= x"0000000" & "0000"; we <= '0'; wait for cpuperiod; -- Configure and starte report "start" severity note; address <= "00" & x"00" ; tseq_IBO <= x"00000001"; we <= '1'; wait for cpuperiod; address <= "00" & x"00" ; tseq_IBO <= x"00000000"; we <= '0'; wait for cpuperiod; wait for 160*cpuperiod; report "sequence using all ouput bits" severity note; we <= '1'; address <= "10" & x"00" ; tseq_IBO <= "00" & x"000000" & '0' & "10101"; wait for cpuperiod; address <= "10" & x"01" ; tseq_IBO <= "00" & x"000000" & '0' & "01010"; wait for cpuperiod; address <= "10" & x"02" ; tseq_IBO <= "00" & x"000000" & '0' & "10101"; wait for cpuperiod; address <= "10" & x"03" ; tseq_IBO <= "00" & x"000000" & '0' & "01010"; wait for cpuperiod; address <= "10" & x"04" ; tseq_IBO <= "00" & x"000000" & '0' & "10101"; wait for cpuperiod; address <= "10" & x"05" ; tseq_IBO <= "00" & x"000001" & '0' & "00001"; wait for cpuperiod; address <= "10" & x"06" ; tseq_IBO <= "00" & x"000001" & '0' & "00010"; wait for cpuperiod; address <= "10" & x"07" ; tseq_IBO <= "00" & x"000001" & '0' & "00100"; wait for cpuperiod; address <= "10" & x"08" ; tseq_IBO <= "00" & x"000001" & '0' & "01000"; wait for cpuperiod; address <= "10" & x"09" ; tseq_IBO <= "00" & x"000001" & '0' & "10000"; wait for cpuperiod; address <= "10" & x"0a" ; tseq_IBO <= "00" & x"000002" & '0' & "11111"; wait for cpuperiod; address <= "10" & x"0b" ; tseq_IBO <= "00" & x"000003" & '0' & "11111"; wait for cpuperiod; address <= "10" & x"0c" ; tseq_IBO <= "00" & x"000004" & '0' & "11111"; wait for cpuperiod; address <= "10" & x"0d" ; tseq_IBO <= "00" & x"000005" & '0' & "11111"; wait for cpuperiod; address <= "10" & x"0e" ; tseq_IBO <= "00" & x"000006" & '0' & "11111"; wait for cpuperiod; address <= "10" & x"0f" ; tseq_IBO <= "00" & x"000007" & '0' & "11111"; wait for cpuperiod; address <= "10" & x"10" ; tseq_IBO <= "00" & x"000008" & '0' & "11111"; wait for cpuperiod; address <= "10" & x"11" ; tseq_IBO <= "00" & x"000009" & '0' & "11111"; wait for cpuperiod; address <= "10" & x"12" ; tseq_IBO <= "00" & x"00002a" & '1' & "10000"; wait for cpuperiod; --end marker -- we <= '0' ; wait for cpuperiod; we <= '1'; address <= "00" & x"00" ; tseq_IBO <= x"00000000"; wait for cpuperiod*4; address <= "00" & x"00" ; tseq_IBO <= x"00000001"; wait for cpuperiod; we <= '0'; wait for 350*cpuperiod; we <= '1'; address <= "10" & x"00" ; tseq_IBO <= "00" & x"000001" & '0' & "00001"; wait for cpuperiod; address <= "10" & x"01" ; tseq_IBO <= "00" & x"000000" & '0' & "00010"; wait for cpuperiod; address <= "10" & x"02" ; tseq_IBO <= "00" & x"000000" & '0' & "00100"; wait for cpuperiod; address <= "10" & x"03" ; tseq_IBO <= "00" & x"000002" & '0' & "01000"; wait for cpuperiod; address <= "10" & x"04" ; tseq_IBO <= "00" & x"000000" & '0' & "01000"; wait for cpuperiod; address <= "10" & x"05" ; tseq_IBO <= "00" & x"000000" & '0' & "01000"; wait for cpuperiod; address <= "10" & x"06" ; tseq_IBO <= "00" & x"000000" & '1' & "10000"; wait for cpuperiod; address <= "00" & x"00" ; tseq_IBO <= x"00000000"; wait for cpuperiod*4; address <= "00" & x"00" ; tseq_IBO <= x"00000002"; wait for cpuperiod; we <= '0'; wait for 3us; we <= '1'; address <= "00" & x"00" ; tseq_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; wait; end process WaveGen_Proc; end dut; ------------------------------------------------------------------------------- configuration trigger_sequencer_tb_dut_cfg of trigger_sequencer_tb is for dut end for; end trigger_sequencer_tb_dut_cfg; -------------------------------------------------------------------------------