-------------------------------------------------------------------------------
-- Title      : Testbench for design "triggerLUT"
-- Project    : 
-------------------------------------------------------------------------------
-- File       : triggerLUT_tb.vhd
-- Author     : tkrawuts
-- Company    : 
-- Created    : 2009-04-14
-- Last update: 2009-04-17
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2009 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2009-04-14  1.0      tkrawuts        Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-------------------------------------------------------------------------------

entity triggerLUT_tb is

end triggerLUT_tb;

-------------------------------------------------------------------------------

architecture DUT of triggerLUT_tb is

  component triggerLUT
    port (
      inputclk        : in  std_logic;
      dataclk         : in  std_logic;
      resetn          : in  std_logic;
      triggerin       : in  std_logic_vector(575 downto 0);
      triggerout      : out std_logic_vector(7 downto 0);
      datain          : in  std_logic_vector(31 downto 0);
      triggerLUT1_OBI : out std_logic_vector(31 downto 0);
      triggerLUT2_OBI : out std_logic_vector(31 downto 0);
      triggerLUT3_OBI : out std_logic_vector(31 downto 0);
      addr            : in  std_logic_vector(12 downto 0);
      triggerLUT_we   : in  std_logic);
  end component;

  -- component ports
  signal inputclk        : std_logic;
  signal dataclk         : std_logic;
  signal resetn          : std_logic;
  signal triggerin       : std_logic_vector(575 downto 0);
  signal triggerout      : std_logic_vector(7 downto 0);
  signal datain          : std_logic_vector(31 downto 0);
  signal triggerLUT1_OBI : std_logic_vector(31 downto 0);
  signal triggerLUT2_OBI : std_logic_vector(31 downto 0);
  signal triggerLUT3_OBI : std_logic_vector(31 downto 0);
  signal addr            : std_logic_vector(12 downto 0);
  signal triggerLUT_we   : std_logic;

  -- clock

  signal en_trigger : std_logic;
  signal tgi : std_logic_vector(575 downto 0);


  signal Clk : std_logic := '1';
  signal Clkslow  : std_logic := '1';
  constant pslow : time := 12000 ps;
  constant perislow : time := pslow*2;
  constant p120 : time      := 4000 ps;
  constant peri : time      := p120*2;



  
begin  -- DUT

  -- component instantiation
  DUT : triggerLUT
    port map (
      inputclk        => Clk,
      dataclk         => Clk,
      resetn          => resetn,
      triggerin       => triggerin,
      triggerout      => triggerout,
      datain          => datain,
      triggerLUT1_OBI => triggerLUT1_OBI,
      triggerLUT2_OBI => triggerLUT2_OBI,
      triggerLUT3_OBI => triggerLUT3_OBI,
      addr            => addr,
      triggerLUT_we   => triggerLUT_we);

  -- clock generation
  Clk <= not Clk after p120;
  Clkslow <= not Clkslow after pslow;
  -- waveform generation
  WaveGen_Proc : process
  begin
    -- insert signal assignments here
    resetn        <= '1';
    datain        <= x"00000000";
    addr          <= '0' & x"000";
    triggerLUT_we <= '0';
    en_trigger <= '0';
    wait for 5*peri;

    resetn <= '0'; wait for 2*peri;
    resetn <= '1'; wait for 2*peri;

    -- stage 1:
    addr <= "000" & "0000000000"; datain <= x"aaa0aaaa"; triggerLUT_we <= '1'; wait for 2*peri;
    addr <= '0' & x"000"; datain <= x"00000000"; triggerLUT_we <= '0'; wait for 2*peri;
    -- stage 1b:
    addr <= "000" & "0000000001"; datain <= x"00000004"; triggerLUT_we <= '1'; wait for 2*peri;
    addr <= '0' & x"000"; datain <= x"00000000"; triggerLUT_we <= '0'; wait for 2*peri;
    -- stage 1c:
    addr <= "000" & "0000000010"; datain <= x"00000004"; triggerLUT_we <= '1'; wait for 2*peri;
    addr <= '0' & x"000"; datain <= x"00000000"; triggerLUT_we <= '0'; wait for 2*peri;

    -- stage 2: 
    addr <= "110" & "0000000000"; datain <= x"00000001"; triggerLUT_we <= '1'; wait for 2*peri;
    addr <= '0' & x"000"; datain <= x"00000000"; triggerLUT_we <= '0'; wait for 2*peri;
    -- stage 3:
    addr <= "111" & "0000000000"; datain <= x"00000001"; triggerLUT_we <= '1'; wait for 2*peri;
    addr <= '0' & x"000"; datain <= x"00000000"; triggerLUT_we <= '0'; wait for 2*peri;
    en_trigger <= '1';
    wait;
    
  end process WaveGen_Proc;

--  triggerin_p : process (clkslow, resetn)
--    variable cy : std_logic;
--  begin  
--    if resetn = '0' then                -- asynchronous reset (active low)
--      tgi <= (tgi'high downto tgi'low + 1 => '0', tgi'low => '1');
--      cy        := '1';
--    elsif clkslow'event and clkslow = '1' then  -- rising clock edge
--      if en_trigger='1' then
--        cy        := tgi(tgi'high);
--        tgi <= tgi(tgi'high - 1 downto tgi'low) & cy;      
--      end if;
--    end if;
--  end process triggerin_p;

  tirgcnt: process (Clkslow, resetn)
  begin  -- process tirgcnt
    if resetn = '0' then            -- asynchronous reset (active low)
      tgi <= (tgi'high downto tgi'low => '0');
    elsif Clkslow'event and Clkslow = '1' then  -- rising clock edge
      if en_trigger = '1' then
        tgi <= tgi + '1';        
      end if;
    end if;
  end process tirgcnt;
  
  triggerin <= tgi when en_trigger='1' else (triggerin'high downto triggerin'low => '0');
  

end DUT;

-------------------------------------------------------------------------------

configuration triggerLUT_tb_DUT_cfg of triggerLUT_tb is
  for DUT
  end for;
end triggerLUT_tb_DUT_cfg;

-------------------------------------------------------------------------------