------------------------------------------------------------------------------- -- Title : Testbench for design "mempipe" -- Project : ------------------------------------------------------------------------------- -- File : mempipe_tb.vhd -- Author : U-KRAW\tkrawuts -- Company : -- Created : 2009-10-28 -- Last update: 2009-10-28 -- Platform : -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2009 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2009-10-28 1.0 tkrawuts Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- entity mempipe_tb is end mempipe_tb; ------------------------------------------------------------------------------- architecture dut of mempipe_tb is component mempipe port ( clk40 : in std_logic; cpuclk : in std_logic; reset_n : in std_logic; cpuaddr : in std_logic_vector(8 downto 0); cpudata : in std_logic_vector(31 downto 0); cpuwe : in std_logic; init : in std_logic; done : out std_logic; inca : in std_logic; q : out std_logic_vector(31 downto 0)); end component; -- component ports signal clk40 : std_logic; signal cpuclk : std_logic; signal cpuaddr : std_logic_vector(8 downto 0); signal reset_n : std_logic; signal cpudata : std_logic_vector(31 downto 0); signal cpuwe : std_logic; signal init : std_logic; signal done : std_logic; signal inca : std_logic; signal q : std_logic_vector(31 downto 0); -- clock signal Clki : std_logic := '1'; signal CpuClki : std_logic := '1'; constant period : time := 25 ns; constant halfperiod : time := period/2; constant cpuperiod : time := period/3; constant halfcpuperiod : time := cpuperiod/2; begin -- dut -- component instantiation DUT : mempipe port map ( clk40 => Clki, cpuclk => CpuClki, reset_n => reset_n, cpuaddr => cpuaddr, cpudata => cpudata, cpuwe => cpuwe, init => init, done => done, inca => inca, q => q); -- clock generation -- clock generation Clki <= not Clki after halfperiod; CpuClki <= not CpuClki after halfcpuperiod; -- waveform generation WaveGen_Proc : process begin -- insert signal assignments here cpuaddr <= '0' & x"00"; cpudata <= x"00000000"; cpuwe <= '0'; init <= '0'; inca <= '0'; wait for period; reset_n <= '0'; wait for 3*period; reset_n <= '1'; wait for 6*period; -- Write to seq mem cpuwe <= '1'; cpuaddr <= '0' & x"00"; cpudata <= x"00000010"; wait for cpuperiod; cpuaddr <= '0' & x"01"; cpudata <= x"00000020"; wait for cpuperiod; cpuaddr <= '0' & x"02"; cpudata <= x"00000030"; wait for cpuperiod; cpuaddr <= '0' & x"03"; cpudata <= x"00000040"; wait for cpuperiod; cpuaddr <= '0' & x"04"; cpudata <= x"00000050"; wait for cpuperiod; cpuaddr <= '0' & x"05"; cpudata <= x"00000060"; wait for cpuperiod; cpuaddr <= '0' & x"06"; cpudata <= x"00000070"; wait for cpuperiod; cpuaddr <= '0' & x"07"; cpudata <= x"00000080"; wait for cpuperiod; cpuwe <= '0'; report "for wait" severity note; wait for 8336 ps; -- wait until Clki'posedge; wait for 5 ps; report "nach wait" severity note; wait for 10*period; init <= '1'; wait for period; init <= '0'; wait for 10*period; inca <= '1'; wait for period; inca <= '0'; wait for 10*period; inca <= '1'; wait for period*2; inca <= '0'; wait for 10*period; wait for 10*period; init <= '1'; wait for period; init <= '0'; wait for 10*period; inca <= '1'; wait for period*5; inca <= '0'; wait for 10*period; inca <= '1'; wait for period; inca <= '0'; wait for period; inca <= '1'; wait for period; inca <= '0'; wait for period; inca <= '1'; wait for period; inca <= '0'; wait for period; wait for 10*period; init <= '1'; wait for period; init <= '0'; wait for 10*period; inca <= '1'; wait for period; inca <= '0'; wait for period; inca <= '1'; wait for period; inca <= '0'; wait for period; inca <= '1'; wait for period; inca <= '0'; wait for period; inca <= '1'; wait for period; inca <= '0'; wait for period; inca <= '1'; wait for period; inca <= '0'; wait for period; inca <= '1'; wait for period; inca <= '0'; wait for period; inca <= '1'; wait for period; inca <= '0'; wait for period; inca <= '1'; wait for period; inca <= '0'; wait for period; wait for 10*period; init <= '1'; wait for period; init <= '0'; wait for 10*period; inca <= '1'; wait for period; inca <= '0'; wait for period*2; inca <= '1'; wait for period; inca <= '0'; wait for period*2; inca <= '1'; wait for period; inca <= '0'; wait for period*2; inca <= '1'; wait for period; inca <= '0'; wait for period*2; inca <= '1'; wait for period; inca <= '0'; wait for period*2; inca <= '1'; wait for period; inca <= '0'; wait for period*2; inca <= '1'; wait for period; inca <= '0'; wait for period*2; inca <= '1'; wait for period; inca <= '0'; wait for period*2; wait for 10*period; init <= '1'; wait for period; init <= '0'; wait for 10*period; inca <= '1'; wait for period*2; inca <= '0'; wait for period; inca <= '1'; wait for period*2; inca <= '0'; wait for period; inca <= '1'; wait for period*2; inca <= '0'; wait for period; inca <= '1'; wait for period*2; inca <= '0'; wait for period; wait for 10*period; init <= '1'; wait for period; init <= '0'; wait for 2*period; inca <= '1'; wait for period*4; inca <= '0'; wait for period; wait; end process WaveGen_Proc; end dut; ------------------------------------------------------------------------------- configuration mempipe_tb_dut_cfg of mempipe_tb is for dut end for; end mempipe_tb_dut_cfg; -------------------------------------------------------------------------------