-------------------------------------------------------------------------------
-- Title      : Testbench for design "fsm"
-- Project    : 
-------------------------------------------------------------------------------
-- File       : fsm_tb.vhd
-- Author     : tkrawuts
-- Company    : 
-- Created    : 2009-07-05
-- Last update: 2009-07-05
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2009 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2009-07-05  1.0      tkrawuts        Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------------------------------------

entity fsm_tb is

end fsm_tb;

-------------------------------------------------------------------------------

architecture dut of fsm_tb is

  component fsm
    port (
      clk         : in  std_logic;
      reset_n     : in  std_logic;
      en          : in  std_logic;
      rst         : in  std_logic;
      cnt_en      : out std_logic;
      cnt_srst    : out std_logic;
      memin_zero  : out std_logic;
      we          : out std_logic;
      hold_cntval : out std_logic;
      stateinfo   : out std_logic_vector (2 downto 0);
      address     : out std_logic_vector (9 downto 0));
  end component;

  -- component ports
  signal clk         : std_logic;
  signal reset_n     : std_logic;
  signal en          : std_logic;
  signal rst         : std_logic;
  signal cnt_en      : std_logic;
  signal cnt_srst    : std_logic;
  signal memin_zero  : std_logic;
  signal we          : std_logic;
  signal hold_cntval : std_logic;
  signal stateinfo   : std_logic_vector (2 downto 0);
  signal address     : std_logic_vector (9 downto 0);

  -- clock

  signal Clki : std_logic := '1';

  constant period     : time := 25 ns;
  constant halfperiod : time := period/2;

  constant rstfak : integer := 3;
  constant enfak  : integer := 8;
  constant disfak : integer := 9;
  
begin  -- dut

  -- component instantiation
  DUT : fsm
    port map (
      clk         => Clki,
      reset_n     => reset_n,
      en          => en,
      rst         => rst,
      cnt_en      => cnt_en,
      cnt_srst    => cnt_srst,
      memin_zero  => memin_zero,
      we          => we,
      hold_cntval => hold_cntval,
      stateinfo   => stateinfo,
      address     => address);

  -- clock generation
  Clki <= not Clki after halfperiod;

  -- waveform generation
  WaveGen_Proc : process
  begin
    -- insert signal assignments here
    en      <= '0'; rst <= '0';
    reset_n <= '1';
    wait for period;
    reset_n <= '0';
    wait for 3*period;
    reset_n <= '1';
    wait for 6*period;

    -- 000 -> 001 POR resetting
    wait for 576*rstfak*period;
    wait for 40*period;
    report "reset done" severity note;
    assert stateinfo = "001" report "Reset not done" severity error;
    --  reset done

    -- enabling
    en <= '1'; rst <= '0';
    wait for 576*enfak*period;
    wait for 40*period;
    report "running, counter wrapped once" severity note;
    assert stateinfo = "010" report "Not running" severity error;
    en <= '0'; rst <= '0';

    -- diabling
    wait for 576*disfak*2*period;
    report "disabled" severity note;
    assert stateinfo = "100" report "Not in disabled" severity error;


    -- resetting
    en <= '0'; rst <= '1';
    wait for 40*period;
    en <= '0'; rst <= '0';
    wait for 576*rstfak*period;
    report "reset done" severity note;
    assert stateinfo = "001" report "Reset not done" severity error;


    -- enabling
    en <= '1'; rst <= '0';
    wait for 240*enfak*period;
    report "running, counter wrapped once" severity note;
    assert stateinfo = "010" report "Not running" severity error;
    en <= '0'; rst <= '1';

    -- resetting
    wait for 40*period;
    en <= '0'; rst <= '0';
    wait for 576*rstfak*period;
    report "reset done" severity note;
    assert stateinfo = "001" report "Reset not done" severity error;
    
    -- enabling
    en <= '1'; rst <= '0';
    wait for 240*enfak*period;
    report "running, counter wrapped once" severity note;
    assert stateinfo = "010" report "Not running" severity error;
    en <= '0'; rst <= '0';
    
    -- diabling
    wait for 576*disfak*2*period;
    report "disabled" severity note;
    assert stateinfo = "100" report "Not in disabled" severity error;

    -- enabling
    en <= '1'; rst <= '0';
    wait for 240*enfak*period;
    report "running, counter wrapped once" severity note;
    assert stateinfo = "010" report "Not running" severity error;


    -- Tested state transitions of superior 5 states (=stateinfo) succesfully
    
    wait;
  end process WaveGen_Proc;

  

end dut;

-------------------------------------------------------------------------------

configuration fsm_tb_dut_cfg of fsm_tb is
  for dut
  end for;
end fsm_tb_dut_cfg;

-------------------------------------------------------------------------------