------------------------------------------------------------------------------- -- Title : Testbench for design "cnt576x48" -- Project : ------------------------------------------------------------------------------- -- File : cnt576x48_tb.vhd -- Author : tkrawuts -- Company : -- Created : 2009-07-05 -- Last update: 2009-07-06 -- Platform : -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2009 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2009-07-05 1.0 tkrawuts Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- entity cnt576x48_tb is end cnt576x48_tb; ------------------------------------------------------------------------------- architecture dut of cnt576x48_tb is component cnt576x48 port ( clk : in std_logic; cpuclk : in std_logic; reset_n : in std_logic; S : in std_logic_vector(575 downto 0); we : in std_logic; rd : in std_logic; address : in std_logic_vector(2 downto 0); counter_IBO : in std_logic_vector(31 downto 0); counter_OBI : out std_logic_vector(31 downto 0)); end component; -- component ports signal clk : std_logic; signal cpuclk : std_logic; signal reset_n : std_logic; signal S : std_logic_vector(575 downto 0); signal we : std_logic; signal rd : std_logic; signal address : std_logic_vector(2 downto 0); signal counter_IBO : std_logic_vector(31 downto 0); signal counter_OBI : std_logic_vector(31 downto 0); -- clock signal Clki : std_logic := '1'; signal CpuClki : std_logic := '1'; constant period : time := 25 ns; constant halfperiod : time := period/2; constant cpuperiod : time := period/3; constant halfcpuperiod : time := cpuperiod/2; constant rstfak : integer := 3; constant enfak : integer := 8; constant disfak : integer := 9; begin -- dut -- component instantiation DUT : cnt576x48 port map ( clk => Clki, cpuclk => CpuClki, reset_n => reset_n, S => S, we => we, rd => rd, address => address, counter_IBO => counter_IBO, counter_OBI => counter_OBI); -- clock generation Clki <= not Clki after halfperiod; CpuClki <= not CpuClki after halfcpuperiod; -- waveform generation WaveGen_Proc : process begin -- insert signal assignments here reset_n <= '1'; S <= (others => '0'); we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= (others => '0'); wait for period; reset_n <= '0'; wait for 3*period; reset_n <= '1'; wait for 6*period; -- 000 -> 001 POR resetting wait for 576*rstfak*period; wait for 40*period; report "reset done" severity note; address <= "000"; counter_IBO <= x"00000001"; we <= '1'; wait for cpuperiod; address <= "000"; counter_IBO <= x"00000000"; we <= '0'; wait for 10*period; S <= (S'high downto S'low+2 => '0') & "11"; wait for 3*period; S <= (S'high downto S'low+2 => '0') & "10"; wait for 200*period; we <= '1'; rd <= '0'; address <= "010"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "010"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '1'; address <= "011"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '1'; address <= "100"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '1'; address <= "011"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '1'; address <= "100"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '1'; address <= "011"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '1'; address <= "100"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for 800 us; address <= "000"; counter_IBO <= x"00000000"; we <= '1'; wait for cpuperiod; address <= "000"; counter_IBO <= x"00000000"; we <= '0'; wait for 576*disfak*period; we <= '1'; rd <= '0'; address <= "010"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "010"; counter_IBO <= x"00000000"; wait for cpuperiod*5; we <= '0'; rd <= '1'; address <= "011"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod*5; we <= '0'; rd <= '1'; address <= "100"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod*5; we <= '0'; rd <= '1'; address <= "011"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod*5; we <= '0'; rd <= '1'; address <= "100"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod*5; wait for cpuperiod*5; address <= "000"; counter_IBO <= x"00000002"; we <= '1'; wait for cpuperiod; address <= "000"; counter_IBO <= x"00000000"; we <= '0'; wait for cpuperiod*5; wait for 200 us; address <= "000"; counter_IBO <= x"00000000"; we <= '1'; wait for cpuperiod; address <= "000"; counter_IBO <= x"00000000"; we <= '0'; wait for cpuperiod*5; we <= '1'; rd <= '0'; address <= "010"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "010"; counter_IBO <= x"00000000"; wait for cpuperiod*5; we <= '0'; rd <= '1'; address <= "011"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod*5; we <= '0'; rd <= '1'; address <= "100"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod*5; we <= '0'; rd <= '1'; address <= "011"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod*5; we <= '0'; rd <= '1'; address <= "100"; counter_IBO <= x"00000000"; wait for cpuperiod; we <= '0'; rd <= '0'; address <= "000"; counter_IBO <= x"00000000"; wait for cpuperiod*5; wait; end process WaveGen_Proc; end dut; ------------------------------------------------------------------------------- configuration cnt576x48_tb_dut_cfg of cnt576x48_tb is for dut end for; end cnt576x48_tb_dut_cfg; -------------------------------------------------------------------------------