-------------------------------------------------------------------------------
-- Title      : Testbench for design "baseLUT"
-- Project    : 
-------------------------------------------------------------------------------
-- File       : baseLUT_tb.vhd
-- Author     : tkrawuts
-- Company    : 
-- Created    : 2009-04-13
-- Last update: 2009-04-15
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2009 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2009-04-13  1.0      tkrawuts        Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------------------------------------

entity baseLUT_tb is

end baseLUT_tb;

-------------------------------------------------------------------------------

architecture DUT of baseLUT_tb is

  component baseLUT
    generic (
      inwidth : integer);
    port (
      inputclk   : in  std_logic;
      dataclk    : in  std_logic;
      resetn     : in  std_logic;
      triggerin  : in  std_logic_vector(inwidth-1 downto 0);
      triggerout : out std_logic;
      datain     : in  std_logic_vector(31 downto 0);
      dataout    : out std_logic_vector(31 downto 0);
      addr       : in  std_logic_vector(inwidth-6 downto 0);
      we         : in  std_logic);
  end component;

  -- component generics
  constant inwidth : integer := 12;

  -- component ports
  signal inputclk   : std_logic;
  signal dataclk    : std_logic;
  signal resetn     : std_logic;
  signal triggerin  : std_logic_vector(inwidth-1 downto 0);
  signal triggerout : std_logic;
  signal datain     : std_logic_vector(31 downto 0);
  signal dataout    : std_logic_vector(31 downto 0);
  signal addr       : std_logic_vector(inwidth-6 downto 0);
  signal we         : std_logic;

  -- clock
  signal Clk    : std_logic := '1';
  constant p120 : time      := 4000 ps;
  
begin  -- DUT

  -- component instantiation
  DUT : baseLUT
    generic map (
      inwidth => inwidth)
    port map (
      inputclk   => Clk,
      dataclk    => Clk,
      resetn     => resetn,
      triggerin  => triggerin,
      triggerout => triggerout,
      datain     => datain,
      dataout    => dataout,
      addr       => addr,
      we         => we);

  -- clock generation
  Clk <= not Clk after p120;

  -- waveform generation
  WaveGen_Proc : process
  begin
    -- insert signal assignments here
    
    wait until Clk = '1';
    resetn    <= '1';
    triggerin <= "000000000000";
    datain    <= x"00000000";
    addr      <= "0000000";
    we        <= '0';
    wait for 10*p120;
    datain    <= x"55555555";
    addr      <= "0000000";
    we        <= '1';
    wait for 2*p120;
    we        <= '0';
    wait for 2*p120;
    datain    <= x"aaaaaaaa";
    addr      <= "0000001";
    we        <= '1';
    wait for 2*p120;
    we        <= '0';
    wait for 2*p120;
    datain    <= x"00000010";           -- Set Bit 4 in Address 3 = 0x64 (dec.  100)
    addr      <= "0000011";
    we        <= '1';

    wait for 2*p120;
    we        <= '0';

    wait for 10*p120;
    triggerin <= "000000000001";
    wait for 5*p120;
    triggerin <= "000000000010";
    wait for 5*p120;
    triggerin <= "000000000011";
    wait for 5*p120;
    triggerin <= "000000000100";
    wait for 5*p120;
    triggerin <= "000000000101";
    wait for 5*p120;


    wait for 10*p120;
    triggerin <= "000000100001";
    wait for 5*p120;
    triggerin <= "000000100010";
    wait for 5*p120;
    triggerin <= "000000100011";
    wait for 5*p120;
    triggerin <= "000000100100";
    wait for 5*p120;
    triggerin <= "000000100101";

    wait for 10*p120;
    triggerin <= "000001100001";
    wait for 5*p120;
    triggerin <= "000001100010";
    wait for 5*p120;
    triggerin <= "000001100011";
    wait for 5*p120;
    triggerin <= "000001100100";           -- 0x64 matches one it set above at addr 3
    wait for 5*p120;
    triggerin <= "000001100101";
    
    wait;
  end process WaveGen_Proc;

  

end DUT;

-------------------------------------------------------------------------------

configuration baseLUT_tb_DUT_cfg of baseLUT_tb is
  for DUT
  end for;
end baseLUT_tb_DUT_cfg;

-------------------------------------------------------------------------------