-------------------------------------------------------------------------------
-- Title      : Testbench for design "acnt"
-- Project    : 
-------------------------------------------------------------------------------
-- File       : acnt_tb.vhd
-- Author     : tkrawuts
-- Company    : 
-- Created    : 2009-07-03
-- Last update: 2009-07-03
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2009 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2009-07-03  1.0      tkrawuts	Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------------------------------------

entity acnt_tb is

end acnt_tb;

-------------------------------------------------------------------------------

architecture dut of acnt_tb is

  component acnt
    port (
      clk       : in  std_logic;
      reset_n   : in  std_logic;
      acnt_clr  : in  std_logic;
      acnt_en   : in  std_logic;
      acnt_zero : out std_logic;
      address   : out std_logic_vector (9 downto 0));
  end component;

  -- component ports
  signal clk       : std_logic;
  signal reset_n   : std_logic;
  signal acnt_clr  : std_logic;
  signal acnt_en   : std_logic;
  signal acnt_zero : std_logic;
  signal address   : std_logic_vector (9 downto 0);

  -- clock
  signal Clki : std_logic := '1';

  constant period : time := 10 ns;
  constant halfperiod : time := period/2;

  
begin  -- dut

  -- component instantiation
  DUT: acnt
    port map (
      clk       => Clki,
      reset_n   => reset_n,
      acnt_clr  => acnt_clr,
      acnt_en   => acnt_en,
      acnt_zero => acnt_zero,
      address   => address);

  -- clock generation
  Clki <= not Clki after halfperiod;

  -- waveform generation
  WaveGen_Proc: process
  begin
    -- insert signal assignments here
    reset_n <= '1' ; acnt_clr <= '0' ; acnt_en <= '0';
    wait for period;
    reset_n <= '0' ; acnt_clr <= '0' ; acnt_en <= '0';
    wait for 3*period;
    reset_n <= '1' ; acnt_clr <= '0' ; acnt_en <= '0';
    wait for 6*period;

    acnt_clr <= '0' ; acnt_en <= '1';
    wait for period;
    acnt_clr <= '0' ; acnt_en <= '0';
    wait for 9*period;

    acnt_clr <= '0' ; acnt_en <= '1';
    wait for 2*period;
    acnt_clr <= '0' ; acnt_en <= '0';
    wait for 8*period;


    acnt_clr <= '0' ; acnt_en <= '1';
    wait for 3*period;
    acnt_clr <= '0' ; acnt_en <= '0';
    wait for 7*period;

    acnt_clr <= '1' ; acnt_en <= '1';
    wait for 2*period;
    acnt_clr <= '0' ; acnt_en <= '0';
    wait for 8*period;

    acnt_clr <= '0' ; acnt_en <= '1';
    wait for 575*period;
    acnt_clr <= '0' ; acnt_en <= '0';
    wait for 8*period;

    acnt_clr <= '0' ; acnt_en <= '1';
    wait for period;
    acnt_clr <= '0' ; acnt_en <= '0';
    wait for 9*period;
    
    wait;
    
  end process WaveGen_Proc;

  

end dut;

-------------------------------------------------------------------------------

configuration acnt_tb_dut_cfg of acnt_tb is
  for dut
  end for;
end acnt_tb_dut_cfg;

-------------------------------------------------------------------------------