------------------------------------------------------------------------------- -- Title : Testbench for design "TLMU" -- Project : ------------------------------------------------------------------------------- -- File : TLMU_tb.vhd<2> -- Author : tkrawuts -- Company : -- Created : 2009-03-18 -- Last update: 2011-02-21 -- Platform : -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2009 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2009-03-18 1.0 tkrawuts Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; library UNISIM; use UNISIM.vcomponents.all; use IEEE.STD_LOGIC_TEXTIO.all; use STD.TEXTIO.all; ------------------------------------------------------------------------------- entity TLMU_tb is end TLMU_tb; ------------------------------------------------------------------------------- architecture dut of TLMU_tb is component ser_int generic ( wait_delay : integer := 100; init_delay : integer := 100; file_in : string := "./DATA/sc_send.dat"; file_out : string := "./DATA/sc_recv.dat"); port( reset_n : in std_logic; clk : in std_logic; ready : in std_logic; ser0din : in std_logic; ser0dout : out std_logic ); end component; component TLMU generic ( version_id : std_logic_vector; padCol : positive; padRow : positive); port ( RESET_A : in std_logic; CLK40_A : in std_logic; SCSN_IN_A : in std_logic; SCSN_OUT_A : out std_logic; T_A : out std_logic_vector (7 downto 0); SPA_A : in std_logic; SPB_A : in std_logic; SPC_A : out std_logic; SPD_A : out std_logic; EN_A : in std_logic; RESET_B : in std_logic; CLK40_B : in std_logic; SCSN_IN_B : in std_logic; SCSN_OUT_B : out std_logic; T_B : out std_logic_vector (7 downto 0); SPA_B : in std_logic; SPB_B : in std_logic; SPC_B : out std_logic; SPD_B : out std_logic; EN_B : in std_logic; LED : out std_logic_vector (8 downto 1); SA : in std_logic_vector(padCol*padRow-1 downto 0); SB : in std_logic_vector(padCol*padRow-1 downto 0); T_Data : inout std_logic; T_Clk : out std_logic); end component; -- constant p40 : time := 12500 ps; -- constant p120 : time := 4166.6 ps; constant p40 : time := 12500 ps; constant p120 : time := 12500 ps; -- component generics for ser_int constant wait_delay : integer := 100; constant init_delay : integer := 100; constant file_in : string := "./data/sc_send.dat"; constant file_out : string := "./data/sc_recv.dat"; -- component generics constant version_id : std_logic_vector := x"deadaffe"; constant padCol : positive := 8; constant padRow : positive := 36; -- component ports signal RESET_A : std_logic; signal CLK40_A : std_logic := '1'; signal SCSN_IN_A : std_logic; signal SCSN_OUT_A : std_logic; signal T_A : std_logic_vector (7 downto 0); signal SPA_A : std_logic; signal SPB_A : std_logic; signal SPC_A : std_logic; signal SPD_A : std_logic; signal EN_A : std_logic; signal RESET_B : std_logic; signal CLK40_B : std_logic; signal SCSN_IN_B : std_logic; signal SCSN_OUT_B : std_logic; signal T_B : std_logic_vector (7 downto 0); signal SPA_B : std_logic; signal SPB_B : std_logic; signal SPC_B : std_logic; signal SPD_B : std_logic; signal EN_B : std_logic; signal LED : std_logic_vector (8 downto 1); signal SA : std_logic_vector(padCol*padRow-1 downto 0); signal SB : std_logic_vector(padCol*padRow-1 downto 0); signal T_Data : std_logic; signal T_Clk : std_logic; signal ready : std_logic := '1'; signal clk120 : std_logic := '1'; signal en_trigger : std_logic; signal resetn : std_logic; signal reset : std_logic; signal tgi : std_logic_vector(575 downto 0); signal triggerin : std_logic_vector(575 downto 0); begin -- dut ser_int_1 : ser_int generic map ( wait_delay => wait_delay, init_delay => init_delay, file_in => file_in, file_out => file_out) port map ( reset_n => RESET_A, clk => clk120, ready => ready, ser0din => SCSN_OUT_A, ser0dout => SCSN_IN_A); -- component instantiation DUT : TLMU generic map ( version_id => version_id, padCol => padCol, padRow => padRow) port map ( RESET_A => reset, CLK40_A => CLK40_A, SCSN_IN_A => SCSN_IN_A, SCSN_OUT_A => SCSN_OUT_A, T_A => T_A, SPA_A => SPA_A, SPB_A => SPB_A, SPC_A => SPC_A, SPD_A => SPD_A, EN_A => EN_A, RESET_B => reset, CLK40_B => CLK40_B, SCSN_IN_B => SCSN_IN_B, SCSN_OUT_B => SCSN_OUT_B, T_B => T_B, SPA_B => SPA_B, SPB_B => SPB_B, SPC_B => SPC_B, SPD_B => SPD_B, EN_B => EN_B, LED => LED, SA => SA, SB => SB, T_Data => T_Data, T_Clk => T_Clk); -- clock generation CLK40_A <= not CLK40_A after p40; clk120 <= not clk120 after p120; -- waveform generation WaveGen_Proc : process begin -- insert signal assignments here wait until CLK40_A = '1'; RESET_A <= '0'; SPA_A <= '0'; SPB_A <= '0'; EN_A <= '1'; RESET_B <= '0'; CLK40_B <= '0'; SCSN_IN_B <= '1'; SPA_B <= '0'; SPB_B <= '0'; EN_B <= '0'; -- SA <= (others => '0'); -- SB <= (others => '0'); T_Data <= '1'; T_Clk <= '1'; wait for 2 us; RESET_A <= '1'; wait for 1 us; RESET_A <= '0'; wait for 1 us; RESET_A <= '1'; wait for 50 us; -- SA <= (others => '1'); wait for 2*p120; -- SA <= (others => '0'); wait for 2*p120; -- SA <= (others => '1'); wait; end process WaveGen_Proc; ----------------------------------------------------------------------------- -- Generate Trigger sequence ----------------------------------------------------------------------------- tirgcnt : process (CLK40_A, resetn) begin -- process tirgcnt if resetn = '0' then -- asynchronous reset (active low) tgi <= (tgi'high downto (tgi'low+17) => '0') & "00000000000000000"; elsif CLK40_A'event and CLK40_A = '1' then -- rising clock edge if en_trigger = '1' then tgi <= tgi(tgi'high -1 downto tgi'low) & '1'; end if; end if; end process tirgcnt; ----------------------------------------------------------------------------- -- enable trigger sequencer ----------------------------------------------------------------------------- trigger : process begin -- process trigger en_trigger <= '0'; -- wait for 77 us; -- en_trigger <= '1'; -- wait for 25 ns * 32; -- en_trigger <= '0'; wait; end process trigger; reset <= not RESET_A; resetn <= RESET_A; -- triggerin <= tgi when en_trigger = '1' else ("01" & (triggerin'high-2 downto triggerin'low => '0')); trigger_coinc_stretch_short : process begin triggerin <= (triggerin'high downto triggerin'low => '0'); wait for 103031 ns; triggerin <= (triggerin'high downto triggerin'low+19 => '0') & "1000000000000000001"; wait for 25 ns; triggerin <= (triggerin'high downto triggerin'low => '0'); wait for 200 ns; triggerin <= (triggerin'high downto triggerin'low+19 => '0') & "0000000000000000001"; wait for 25 ns; triggerin <= (triggerin'high downto triggerin'low+19 => '0') & "1000000000000000000"; wait for 25 ns; triggerin <= (triggerin'high downto triggerin'low => '0'); wait; end process trigger_coinc_stretch_short; SA <= not triggerin(287 downto 0); SB <= not triggerin(575 downto 288); end dut; ------------------------------------------------------------------------------- configuration TLMU_tb_dut_cfg of TLMU_tb is for dut end for; end TLMU_tb_dut_cfg; -------------------------------------------------------------------------------