-------------------------------------------------------------------------------
-- Title      : Testbench for design "TA"
-- Project    : 
-------------------------------------------------------------------------------
-- File       : TA_tb.vhd
-- Author     : Tobias Krawutschke
-- Company    : 
-- Created    : 2009-07-13
-- Last update: 2009-07-13
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2009 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2009-07-13  1.0      tkrawuts        Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------------------------------------

entity TA_tb is

end TA_tb;

-------------------------------------------------------------------------------

architecture dut of TA_tb is

  component TA
    port (
      taclk   : in  std_logic;
      scsnclk : in  std_logic;
      reset_n : in  std_logic;
      address : in  std_logic_vector(13 downto 0);
      we      : in  std_logic;
      TA_OBI  : out std_logic_vector;
      TA_IBO  : in  std_logic_vector(31 downto 0);
      S       : in  std_logic_vector(575 downto 0);
      T       : in  std_logic_vector(31 downto 0));
  end component;

  -- component ports
  signal taclk   : std_logic;
  signal scsnclk : std_logic;
  signal reset_n : std_logic;
  signal address : std_logic_vector(13 downto 0);
  signal we      : std_logic;
  signal TA_OBI  : std_logic_vector(31 downto 0);
  signal TA_IBO  : std_logic_vector(31 downto 0);
  signal S       : std_logic_vector(575 downto 0);
  signal T       : std_logic_vector(31 downto 0);

  -- clock
  signal TaClki  : std_logic := '1';
  signal CpuClki : std_logic := '1';

  constant start_addr       : std_logic_vector(13 downto 0) := "11000000000000";
  constant done_ack_addr    : std_logic_vector(13 downto 0) := "11000000000001";
  constant TA_trig_pat_addr : std_logic_vector(13 downto 0) := "11000000000010";
  constant TA_trig_msk_addr : std_logic_vector(13 downto 0) := "11000000000011";
  constant presamples_addr  : std_logic_vector(13 downto 0) := "11000000000100";
  constant startsample_addr : std_logic_vector(13 downto 0) := "11000000000101";
  constant state_addr       : std_logic_vector(13 downto 0) := "11000000000110";

  constant cpuperiod     : time := 25 ns/3;
  constant halfcpuperiod : time := cpuperiod/2;

  constant taperiod     : time := 25 ns /4;
  constant halftaperiod : time := taperiod/2;

begin  -- dut

  -- component instantiation
  DUT : TA
    port map (
      taclk   => TaClki,
      scsnclk => CpuClki,
      reset_n => reset_n,
      address => address,
      we      => we,
      TA_OBI  => TA_OBI,
      TA_IBO  => TA_IBO,
      S       => S,
      T       => T);

  -- clock generation
  TaClki  <= not TaClki  after halftaperiod;
  CpuClki <= not CpuClki after halfcpuperiod;

  -- waveform generation
  WaveGen_Proc : process
  begin
    reset_n <= '1';
    address <= "00" & x"000";
    TA_IBO  <= x"00000000";
    we      <= '0';
    S       <= (others => '0');
    T       <= (others => '0');
    wait for 1 * cpuperiod;
    reset_n <= '0';
    wait for 3 * cpuperiod;
    reset_n <= '1';
    wait for 6 * cpuperiod;
-- reset done after 10* cpuperiod

    -- Write Trigger Pattern Register
    address <= TA_trig_pat_addr; TA_IBO <= x"00000001"; we <= '1';
    wait for 1 * cpuperiod;
    address <= "00" & x"000"; TA_IBO <= x"00000000"; we <= '0';
    wait for 1 * cpuperiod;

    -- Write Trigger Mask Register
    address <= TA_trig_msk_addr; TA_IBO <= x"00000001"; we <= '1';
    wait for 1 * cpuperiod;
    address <= "00" & x"000"; TA_IBO <= x"00000000"; we <= '0';
    wait for 1 * cpuperiod;

    -- Write Presamples
    address <= presamples_addr; TA_IBO <= x"00000064"; we <= '1';
    wait for 1 * cpuperiod;
    address <= "00" & x"000"; TA_IBO <= x"00000000"; we <= '0';
    wait for 1 * cpuperiod;


    
    -- Write Startit
    address <= start_addr; TA_IBO <= x"00000000"; we <= '1';
    wait for 1 * cpuperiod;
    address <= "00" & x"000"; TA_IBO <= x"00000000"; we <= '0';
    wait for 1 * cpuperiod;
    wait for 120 * cpuperiod;

    T <= x"ffffffff"; wait for 3*taperiod;
    T <= x"00000000"; wait for 3*taperiod;    
    T <= x"ffffffff"; wait for 3*taperiod;
    T <= x"00000000"; wait for 3*taperiod;    

    
    wait for taperiod * 512;

    wait for 10 * cpuperiod;

    -- Write Done_ckt
    address <= done_ack_addr; TA_IBO <= x"00000000"; we <= '1';
    wait for 1 * cpuperiod;
    address <= "00" & x"000"; TA_IBO <= x"00000000"; we <= '0';
    wait for 1 * cpuperiod;
    
    -- Read memory from address (18) 
    address <= "10010000000000";    wait for 1 * cpuperiod;
    address <= "10010000000001";    wait for 1 * cpuperiod;
    address <= "10010000000010";    wait for 1 * cpuperiod;
    address <= "10010000000011";    wait for 1 * cpuperiod;
    address <= "10010000000100";    wait for 1 * cpuperiod;
    address <= "10010000000101";    wait for 1 * cpuperiod;
    address <= "10010010100000";    wait for 1 * cpuperiod;
    address <= "10010010100001";    wait for 1 * cpuperiod;
    address <= "10010010100010";    wait for 1 * cpuperiod;
    address <= "10010010100011";    wait for 1 * cpuperiod;            
    address <= "10010010100100";    wait for 1 * cpuperiod;
    address <= "10010010100101";    wait for 1 * cpuperiod;
    address <= "10010010100110";    wait for 1 * cpuperiod;
    address <= "10010010100111";    wait for 1 * cpuperiod;
    
    
    wait;
  end process WaveGen_Proc;

  

end dut;

-------------------------------------------------------------------------------

configuration TA_tb_dut_cfg of TA_tb is
  for dut
  end for;
end TA_tb_dut_cfg;

-------------------------------------------------------------------------------