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-- Title      : Testbench for design "LUT4in1out"
-- Project    : 
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-- File       : LUT4in1out_tb.vhd
-- Author     : tkrawuts
-- Company    : 
-- Created    : 2009-04-14
-- Last update: 2009-04-14
-- Platform   : 
-- Standard   : VHDL'87
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-- Description: 
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-- Copyright (c) 2009 
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-- Revisions  :
-- Date        Version  Author  Description
-- 2009-04-14  1.0      tkrawuts	Created
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library ieee;
use ieee.std_logic_1164.all;

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entity LUT4in1out_tb is

end LUT4in1out_tb;

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architecture DUT of LUT4in1out_tb is

  component LUT4in1out
    port (
      dataclk    : in  std_logic;
      resetn     : in  std_logic;
      triggerin  : in  std_logic_vector(3 downto 0);
      triggerout : out std_logic;
      datain     : in  std_logic_vector(31 downto 0);
      dataout    : out std_logic_vector(31 downto 0);
      we         : in  std_logic);
  end component;

  -- component ports
  signal dataclk    : std_logic;
  signal resetn     : std_logic;
  signal triggerin  : std_logic_vector(3 downto 0);
  signal triggerout : std_logic;
  signal datain     : std_logic_vector(31 downto 0);
  signal dataout    : std_logic_vector(31 downto 0);
  signal we         : std_logic;

  -- clock
  signal Clk : std_logic := '1';

begin  -- DUT

  -- component instantiation
  DUT: LUT4in1out
    port map (
      dataclk    => Clk,
      resetn     => resetn,
      triggerin  => triggerin,
      triggerout => triggerout,
      datain     => datain,
      dataout    => dataout,
      we         => we);

  -- clock generation
  Clk <= not Clk after 10 ns;

  -- waveform generation
  WaveGen_Proc: process
  begin
    -- insert signal assignments here
    
    wait until Clk = '1';
    resetn <= '1';
    we <= '0';
    triggerin <= x"0";
    datain <= x"00000000";
    wait for 100 ns; resetn <= '0'; wait for 100 ns; resetn <= '1'; wait for 100 ns;
    datain <= x"88880110"; we <= '1' ; wait for 20 ns;
    datain <= x"00000000"; we <= '0' ;
    wait for 100 ns;
    triggerin <= x"0"; wait for 100 ns;
    triggerin <= x"1"; wait for 100 ns;
    triggerin <= x"2"; wait for 100 ns;    
    triggerin <= x"3"; wait for 100 ns;
    triggerin <= x"4"; wait for 100 ns;
    triggerin <= x"5"; wait for 100 ns;
    triggerin <= x"6"; wait for 100 ns;
    triggerin <= x"7"; wait for 100 ns;
    triggerin <= x"8"; wait for 100 ns;
    triggerin <= x"9"; wait for 100 ns;
    triggerin <= x"a"; wait for 100 ns;
    triggerin <= x"b"; wait for 100 ns;
    triggerin <= x"c"; wait for 100 ns;
    triggerin <= x"d"; wait for 100 ns;
    triggerin <= x"e"; wait for 100 ns;
    triggerin <= x"f"; wait for 100 ns;
    wait;
  end process WaveGen_Proc;

  

end DUT;

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configuration LUT4in1out_tb_DUT_cfg of LUT4in1out_tb is
  for DUT
  end for;
end LUT4in1out_tb_DUT_cfg;

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