-------------------------------------------------------------------------------
-- Temperature Sensor Register Set to access CLK/DATA_IO
-- Address space: single  Address, Bits 2..0 are used:
--   0: R/W T_Clk output
--   1: R/W T_Data output (0 = drive active 0, 1 = tristate output)
--   2: R/O T_Data input (Bit 1 must be set to 1 to be able to read)
-------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity tsens is
  
  port (
    clk       : in    std_logic;        -- scsn_clk
    reset_n   : in    std_logic;
    we        : in    std_logic;
    tsens_IBO : in    std_logic_vector(31 downto 0);
    tsens_OBI : out   std_logic_vector(31 downto 0);
    T_Data    : inout std_logic;
    T_Clk     : out   std_logic);

end tsens;

architecture behv of tsens is
  signal clkreg : std_logic;
  signal doreg  : std_logic;
  signal direg : std_logic;

begin  -- behv

  clkreg_p: process (clk, reset_n)
  begin  -- process clkreg_p
    if reset_n = '0' then               -- asynchronous reset (active low)
      clkreg <= '0';
      doreg <= '1';
    elsif clk'event and clk = '1' then  -- rising clock edge
      if we='1' then
        clkreg <= tsens_IBO(0);
        doreg <= tsens_IBO(1);        
      end if;
    end if;
  end process clkreg_p;
  
  di_p : process (clk)
  begin  -- process sel_p
    if clk'event and clk = '1' then  -- rising clock edge
      direg <= T_Data;
    end if;
  end process di_p;

  tsens_OBI <= (31 downto 3 => '0') & direg & doreg & clkreg;

  T_Clk <= clkreg;
  T_Data <= 'Z' when doreg = '1' else '0';
  
  
end behv;