-------------------------------------------------------------------------------
-- Mask out input Bits. 1: enabled , 0: disabled
-- 576 Bits organised in 18x32 Bit registers. Address 0,  Bit  0: S(0)
--                                            Address 8,  Bit 31: S(287) = SA(287)
--                                            Address 9,  Bit  0: S(288)
--                                            Address 17, Bit 32: S(575) = SB(287)
--
-- Addressoffset defined in adremux!
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity trigger_input_mask is

  generic(
    width : integer := 576
    );
  port (
    reset_n  : in  std_logic;
    clk      : in  std_logic;
    S_in     : in  std_logic_vector(width-1 downto 0);
    S_out    : out std_logic_vector(width-1 downto 0);
    we       : in  std_logic;
    address  : in  std_logic_vector(4 downto 0);
    mask_IBO : in  std_logic_vector(31 downto 0);
    mask_OBI : out std_logic_vector(31 downto 0)
    );

end trigger_input_mask;

architecture behv of trigger_input_mask is

  signal masksig : std_logic_vector(width-1 downto 0);

  subtype mask_out is std_logic_vector(31 downto 0);
  type mask_arr is array(0 to 31) of mask_out;
  signal mask_reg : mask_arr;

  signal adi : integer range 0 to 31;  -- address in integer

  
begin  -- behv

  
  adi <= conv_integer(address);

  -- Generate 18 Registers a 32 Bit
  regs : for i in 0 to 17 generate
    maskreg : process (clk, reset_n)
    begin  -- PROCESS maskreg
      if reset_n = '0' then               -- asynchronous reset (active low)
        mask_reg(i) <= (others => '0');
      elsif clk'event and clk = '1' then  -- rising clock edge
        if we = '1' and adi = i then
          mask_reg(i) <= mask_IBO;
        end if;
      end if;
    end process maskreg;
    
  end generate regs;

  -- Concatenate the 18 Registers to one mask signal
  mask_concat : for i in 0 to 17 generate
    masksig((i*32)+31 downto (i*32)) <= mask_reg(i);
  end generate mask_concat;
  -- Mask output
  S_out <= S_in and masksig;

  -- demux output for readback to SCSN Bus
  mask_OBI <= mask_reg(adi);
  
end behv;