-- if enable=1 an input signal ('1') longer than 25 ns will be skiped. Input must
-- change once to '0' generate a new output. -> Maximum trigger frequeny: 20MHz

library ieee;
use ieee.std_logic_1164.all;

entity signal_shorter is
  
  port (
    clk40   : in  std_logic;
    reset_n : in  std_logic;
    enable  : in  std_logic;
    bitin   : in  std_logic;
    bitout  : out std_logic);

end signal_shorter;

architecture behv of signal_shorter is

  signal r : std_logic;

begin  -- behv

  reg_p : process (clk40, reset_n)
  begin  -- process reg_p
    if reset_n = '0' then                   -- asynchronous reset (active low)
      r <= '0';
    elsif clk40'event and clk40 = '1' then  -- rising clock edge
      r <= not bitin;
    end if;
  end process reg_p;

  with enable select
    bitout <=
    (r and bitin) when '1',
    bitin         when others;
  
end behv;