-- Assuming cntclk=cpuclk

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity sector_rate_counter is
  
  port (
    cntclk    : in  std_logic;
    cpuclk    : in  std_logic;
    reset_n   : in  std_logic;
    address   : in  std_logic_vector(5 downto 0);
    rate_OBI  : out std_logic_vector(31 downto 0);
    Smasked   : in  std_logic_vector(575 downto 0);
    Ssynced40 : in  std_logic_vector(575 downto 0));

end sector_rate_counter;


architecture behv of sector_rate_counter is


  component orx
    generic (
      width : integer);
    port (
      i : in  std_logic_vector(width-1 downto 0);
      o : out std_logic);
  end component;

  component rate_counter
    generic (
      gate_time : integer;
      fcnt      : integer);
    port (
      cntclk      : in  std_logic;
      cpuclk      : in  std_logic;
      reset_n     : in  std_logic;
      address     : in  std_logic_vector(1 downto 0);
      ratecnt_OBI : out std_logic_vector(31 downto 0);
      T           : in  std_logic);
  end component;

  signal masked_ored   : std_logic_vector(17 downto 0);
  signal unmasked_ored : std_logic_vector(17 downto 0);

  subtype rate_out_st is std_logic_vector(31 downto 0);
  type cnt_arr is array(0 to 31) of rate_out_st;  -- 0 to 17 is ok, the unused 14 will be synthesized away
  signal masked_cnt   : cnt_arr;
  signal unmasked_cnt : cnt_arr;

  signal masked_out, unmasked_out : std_logic_vector(31 downto 0);
  
begin  -- behv

  gen_ors : for i in 0 to 17 generate
    orx_1 : orx
      generic map (width => 32)
      port map (i        => Smasked((i*32)+31 downto (i*32)), o => masked_ored(i));
    orx_2 : orx
      generic map (width => 32)
      port map (i        => Ssynced40((i*32)+31 downto (i*32)), o => unmasked_ored(i));

    rate_counter_masked : rate_counter
      generic map (
        gate_time => 1,
        fcnt      => 40000000)
      port map (
        cntclk      => cntclk,
        cpuclk      => cpuclk,
        reset_n     => reset_n,
        address     => "00",
        ratecnt_OBI => masked_cnt(i),
        T           => masked_ored(i));

    rate_counter_unmasked : rate_counter
      generic map (
        gate_time => 1,
        fcnt      => 40000000)
      port map (
        cntclk      => cntclk,
        cpuclk      => cpuclk,
        reset_n     => reset_n,
        address     => "00",
        ratecnt_OBI => unmasked_cnt(i),
        T           => unmasked_ored(i));

  end generate gen_ors;

  masked_out   <= masked_cnt(conv_integer(address(4 downto 0)));
  unmasked_out <= unmasked_cnt(conv_integer(address(4 downto 0)));

  rate_OBI <= masked_out when address(5)='1' else unmasked_out;
  
end behv;