-- Output switch
-- 8 Trigger Outputs
-- 32 Trigger Inputs
-- select for each ouptut (Address 0..7)
-- which input to select (0..31 = 5 Bit)
--
-- Reset: Output 7..0 are mapped to input 7..0

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity output_switch is
  
  port (
    cpuclk      : in  std_logic;
    reset_n     : in  std_logic;
    oswitch_IBO : in  std_logic_vector(31 downto 0);
    oswitch_OBI : out std_logic_vector(31 downto 0);
    we          : in  std_logic;
    address     : in  std_logic_vector(2 downto 0);
    Tout        : out std_logic_vector(7 downto 0);
    Tin         : in  std_logic_vector(31 downto 0));

end output_switch;

architecture behv of output_switch is

  subtype reg_st is std_logic_vector(4 downto 0);
  type reg_arr is array(0 to 7) of reg_st;
  signal reg : reg_arr;
  
begin  -- behv

  -- Register set
  reg_gen: for i in 0 to 7 generate
    ii: process (cpuclk, reset_n)
    begin  -- process ii
      if reset_n = '0' then             -- asynchronous reset (active low)
        reg(i) <= conv_std_logic_vector(i,5);
      elsif cpuclk'event and cpuclk = '1' then  -- rising clock edge
        if conv_integer(address) = i and we='1' then
          reg(i) <= oswitch_IBO(4 downto 0);
        end if;
      end if;
    end process ii;

    -- Multiplexer;
    Tout(i) <= Tin(conv_integer(reg(i)));
    
  end generate reg_gen;

  oswitch_OBI <= (31 downto 5 => '0') & reg(conv_integer(address));

end behv;