-- Selected Device : 4vlx40ff1148-11 

--  Number of Slices:                       1  out of  18432     0%  
--  Number of 4 input LUTs:                 2  out of  36864     0%  
--  Number of IOs:                          5
--  Number of bonded IOBs:                  5  out of    640     0%


--  All values displayed in nanoseconds (ns)

-- Pad to Pad
-- ---------------+---------------+---------+
-- Source Pad     |Destination Pad|  Delay  |
-- ---------------+---------------+---------+
-- vec_in<0>      |vec_out<0>     |    5.988|
-- vec_in<0>      |vec_out<1>     |    6.174|
-- vec_in<1>      |vec_out<0>     |    5.956|
-- vec_in<1>      |vec_out<1>     |    6.145|
-- vec_in<2>      |vec_out<0>     |    6.165|
-- vec_in<2>      |vec_out<1>     |    6.354|
-- ---------------+---------------+---------+



library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity cntonesLUT3 is
  
  port (
    invec  : in  std_logic_vector(2 downto 0);
    outvec : out std_logic_vector(1 downto 0));

end cntonesLUT3;

architecture behv of cntonesLUT3 is

begin  -- behv

  with invec select
    outvec <=
    "00" when "000",
    "01" when "001" | "010" | "100",
    "10" when "011" | "101" | "110",
    "11" when others;


end behv;