library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

-- Instantiated multiple times from Line 00- to Line 16-17 (top)

entity coinc_line is
  
  generic (
    firstx : integer := 1;
    lastx  : integer := 17;
    awidth : integer := 5);

  port (
    clk     : in  std_logic;
    reset_n : in  std_logic;
    address : in  std_logic_vector(awidth-1 downto 0);
    we      : in  std_logic;
    d       : in  std_logic;            -- from Bus (1 to set matrixpoint)
    dout    : out std_logic;            -- to Bus 
    yin     : in  std_logic;
    xin     : in  std_logic_vector(17 downto 0);
    trigger : out std_logic);



end coinc_line;


architecture behv of coinc_line is

  constant lv_zero    : std_logic_vector(lastx downto firstx) := (others => '0');
  signal line_reg : std_logic_vector(lastx downto firstx);
--  signal line_reg     : std_logic_vector(17 downto 0);
  signal line_val     : std_logic_vector(lastx downto firstx);
  signal trigger_line : std_logic;
  signal dout_vector  : std_logic_vector((2**awidth)-1 downto 0);
  
begin  -- behv

  cellgen : for i in firstx to lastx generate

    mcell_reg : process (clk, reset_n)
    begin  -- process mcell_reg
      if reset_n = '0' then               -- asynchronous reset (active low)
        line_reg(i) <= '0';
      elsif clk'event and clk = '1' then  -- rising clock edge
        if we = '1' and conv_integer(address) = i then
          line_reg(i) <= d;
        end if;
      end if;
    end process mcell_reg;

    line_val(i) <= line_reg(i) and xin(i);
    
  end generate cellgen;

  trigger_line <= '1' when (line_val /= lv_zero) else '0';
  trigger      <= trigger_line and yin;
  -- Warning: Index value(s) does not match array range, simulation mismatch
  -- May introduce Registered?
--  process(clk)
--    begin
--        if rising_edge(clk) then
----          dout <= line_reg(conv_integer(address));
--        end if;
--    end process;

  genov1: for i in 0 to firstx-1 generate
    dout_vector(i) <= '-';
  end generate genov1;

  genov2: for i in firstx to lastx generate
    dout_vector(i) <= line_reg(i);
  end generate genov2;

  genov3: for i in lastx+1 to (2**awidth-1) generate
    dout_vector(i) <= '-';
  end generate genov3;
  dout <= dout_vector(conv_integer(address));
  
end behv;