library IEEE;
use IEEE.STD_LOGIC_1164.all;

library UNISIM;
use UNISIM.vcomponents.all;

entity TLMU_clk is

  port (
    I_A      : in  std_logic;
    I_B      : in  std_logic;
    clocksel   : in std_logic;
    O40    : out std_logic;
    O160   : out std_logic;
    O120   : out std_logic;
    OCLKTA : out std_logic);

end TLMU_clk;

architecture behv of TLMU_clk is

  signal clkin     : std_logic;
  signal clkfxa160 : std_logic; 
    signal clkfxa120 : std_logic;
    signal clkfxta : std_logic;  


  signal CLK0 : std_logic; 
  signal CLK0b : std_logic;
  signal CLK0c : std_logic;

  
begin

  BUFGMUX_VIRTEX4_inst : BUFGMUX_VIRTEX4
    port map (
      O  => clkin,                      -- Clock MUX output
      I0 => I_A,                    -- Clock0 input
      I1 => I_B,                    -- Clock1 input
      S  => clocksel                         -- Clock select input
      );
  

  BUFGinst1 : BUFG
    port map(
      O => O160,
      I => clkfxa160);

  BUFGinst2 : BUFG
    port map(
      O => O40,
      I => CLK0);

  BUFGinst3 : BUFG
    port map(
      O => O120,
      I => clkfxa120);

  BUFGinst5 : BUFG
    port map(
      O => OCLKTA,
      I => clkfxta);

  

    -- DCM_BASE: Base Digital Clock Manager Circuit
    --           Virtex-4/5
    -- Xilinx HDL Language Template, version 9.1.3i

    DCM_BASE_inst_160 : DCM_BASE
    generic map (
      CLKDV_DIVIDE          => 2.0,  -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
      --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE          => 1,       -- Can be any interger from 1 to 32
      CLKFX_MULTIPLY        => 4,       -- Can be any integer from 2 to 32
      CLKIN_DIVIDE_BY_2     => false,  -- TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD          => 25.0,  -- Specify period of input clock in ns from 1.25 to 1000.00
      CLKOUT_PHASE_SHIFT    => "NONE",  -- Specify phase shift mode of NONE or FIXED
      CLK_FEEDBACK          => "1X",    -- Specify clock feedback of NONE or 1X
      DCM_AUTOCALIBRATION   => true,  -- DCM calibrartion circuitry TRUE/FALSE
      DCM_PERFORMANCE_MODE  => "MAX_SPEED",  -- Can be MAX_SPEED or MAX_RANGE
      DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",  -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                        --   an integer from 0 to 15
      DFS_FREQUENCY_MODE    => "LOW",  -- LOW or HIGH frequency mode for frequency synthesis
      DLL_FREQUENCY_MODE    => "LOW",  -- LOW, HIGH, or HIGH_SER frequency mode for DLL
      DUTY_CYCLE_CORRECTION => true,    -- Duty cycle correction, TRUE or FALSE
      FACTORY_JF            => X"F0F0",  -- FACTORY JF Values Suggested to be set to X"F0F0" 
      PHASE_SHIFT           => 0,  -- Amount of fixed phase shift from -255 to 1023
      STARTUP_WAIT          => false)  -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
    port map (
      CLK0     => CLK0,                 -- 0 degree DCM CLK ouptput
      CLK180   => open,                 -- 180 degree DCM CLK output
      CLK270   => open,                 -- 270 degree DCM CLK output
      CLK2X    => open,                 -- 2X DCM CLK output
      CLK2X180 => open,                 -- 2X, 180 degree DCM CLK out
      CLK90    => open,                 -- 90 degree DCM CLK output
      CLKDV    => open,                 -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX    => clkfxa160,            -- DCM CLK synthesis out (M/D)
      CLKFX180 => open,                 -- 180 degree CLK synthesis out
      LOCKED   => open,                 -- DCM LOCK status output
      CLKFB    => CLK0,                 -- DCM clock feedback
      CLKIN    => clkin,           -- Clock input (from IBUFG, BUFG or DCM)
      RST      => '0'                   -- DCM asynchronous reset input
      );

    -- DCM_BASE: Base Digital Clock Manager Circuit
    --           Virtex-4/5
    -- Xilinx HDL Language Template, version 9.1.3i

    DCM_BASE_inst_120 : DCM_BASE
          generic map (
            CLKDV_DIVIDE          => 2.0,  -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
            --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
            CLKFX_DIVIDE          => 1,  -- Can be any interger from 1 to 32
            CLKFX_MULTIPLY        => 3,  -- Can be any integer from 2 to 32
            CLKIN_DIVIDE_BY_2     => false,  -- TRUE/FALSE to enable CLKIN divide by two feature
            CLKIN_PERIOD          => 25.0,  -- Specify period of input clock in ns from 1.25 to 1000.00
            CLKOUT_PHASE_SHIFT    => "NONE",  -- Specify phase shift mode of NONE or FIXED
            CLK_FEEDBACK          => "1X",  -- Specify clock feedback of NONE or 1X
            DCM_AUTOCALIBRATION   => true,  -- DCM calibrartion circuitry TRUE/FALSE
            DCM_PERFORMANCE_MODE  => "MAX_SPEED",  -- Can be MAX_SPEED or MAX_RANGE
            DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",  -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                        --   an integer from 0 to 15
            DFS_FREQUENCY_MODE    => "LOW",  -- LOW or HIGH frequency mode for frequency synthesis
            DLL_FREQUENCY_MODE    => "LOW",  -- LOW, HIGH, or HIGH_SER frequency mode for DLL
            DUTY_CYCLE_CORRECTION => true,  -- Duty cycle correction, TRUE or FALSE
            FACTORY_JF            => X"F0F0",  -- FACTORY JF Values Suggested to be set to X"F0F0" 
            PHASE_SHIFT           => 0,  -- Amount of fixed phase shift from -255 to 1023
            STARTUP_WAIT          => false)  -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
          port map (
            CLK0     => CLK0b,          -- 0 degree DCM CLK ouptput
            CLK180   => open,           -- 180 degree DCM CLK output
            CLK270   => open,           -- 270 degree DCM CLK output
            CLK2X    => open,           -- 2X DCM CLK output
            CLK2X180 => open,           -- 2X, 180 degree DCM CLK out
            CLK90    => open,           -- 90 degree DCM CLK output
            CLKDV    => open,           -- Divided DCM CLK out (CLKDV_DIVIDE)
            CLKFX    => clkfxa120,      -- DCM CLK synthesis out (M/D)
            CLKFX180 => open,           -- 180 degree CLK synthesis out
            LOCKED   => open,           -- DCM LOCK status output
            CLKFB    => CLK0b,          -- DCM clock feedback
            CLKIN    => clkin,  -- Clock input (from IBUFG, BUFG or DCM)
            RST      => '0'             -- DCM asynchronous reset input
            );


  DCM_BASE_inst_TA : DCM_BASE
    generic map (
      CLKDV_DIVIDE          => 2.0,  -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
      --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE          => 1,       -- Can be any interger from 1 to 32
      CLKFX_MULTIPLY        => 5,       -- Can be any integer from 2 to 32
      CLKIN_DIVIDE_BY_2     => false,  -- TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD          => 25.0,  -- Specify period of input clock in ns from 1.25 to 1000.00
      CLKOUT_PHASE_SHIFT    => "NONE",  -- Specify phase shift mode of NONE or FIXED
      CLK_FEEDBACK          => "1X",    -- Specify clock feedback of NONE or 1X
      DCM_AUTOCALIBRATION   => true,  -- DCM calibrartion circuitry TRUE/FALSE
      DCM_PERFORMANCE_MODE  => "MAX_SPEED",  -- Can be MAX_SPEED or MAX_RANGE
      DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",  -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                        --   an integer from 0 to 15
      DFS_FREQUENCY_MODE    => "LOW",  -- LOW or HIGH frequency mode for frequency synthesis
      DLL_FREQUENCY_MODE    => "LOW",  -- LOW, HIGH, or HIGH_SER frequency mode for DLL
      DUTY_CYCLE_CORRECTION => true,    -- Duty cycle correction, TRUE or FALSE
      FACTORY_JF            => X"F0F0",  -- FACTORY JF Values Suggested to be set to X"F0F0" 
      PHASE_SHIFT           => 0,  -- Amount of fixed phase shift from -255 to 1023
      STARTUP_WAIT          => false)  -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
    port map (
      CLK0     => CLK0c,                -- 0 degree DCM CLK ouptput
      CLK180   => open,                 -- 180 degree DCM CLK output
      CLK270   => open,                 -- 270 degree DCM CLK output
      CLK2X    => open,                 -- 2X DCM CLK output
      CLK2X180 => open,                 -- 2X, 180 degree DCM CLK out
      CLK90    => open,                 -- 90 degree DCM CLK output
      CLKDV    => open,                 -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX    => clkfxta,            -- DCM CLK synthesis out (M/D)
      CLKFX180 => open,                 -- 180 degree CLK synthesis out
      LOCKED   => open,                 -- DCM LOCK status output
      CLKFB    => CLK0c,                -- DCM clock feedback
      CLKIN    => clkin,           -- Clock input (from IBUFG, BUFG or DCM)
      RST      => '0'                   -- DCM asynchronous reset input
      );


end behv;