Release 9.1.03i - xst J.33 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./ise/xst/projnav.tmp CPU : 0.00 / 2.69 s | Elapsed : 0.00 / 3.00 s --> Parameter xsthdpdir set to ./ise/xst CPU : 0.00 / 2.69 s | Elapsed : 0.00 / 3.00 s --> Reading design: script/files.txt TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) Partition Resource Summary 9.3) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "script/files.txt" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "./ise/top" Output Format : NGC Target Device : xc4vlx40-11-ff1148 ---- Source Options Top Module Name : TLMU Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Asynchronous To Synchronous : NO Use DSP Block : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 32 Number of Regional Clock Buffers : 32 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Power Reduction : NO Library Search Order : script/lso.txt Keep Hierarchy : NO RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/orx.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/sfr_filter.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/asyncin.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/TLMU_clk.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/trigger_input_sort.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/trigger_input_filter.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/or576.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/TLMU.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ) with generics. padCol = 8 padRow = 36 version_id = "00000000000000010000000000000001" Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ) with generics. oreg = true use_asy = true use_sfr = false Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ) with generics. oreg = true Analyzing hierarchy for entity in library (architecture ) with generics. width = 32 Analyzing hierarchy for entity in library (architecture ) with generics. width = 18 ========================================================================= * HDL Analysis * ========================================================================= Analyzing generic Entity in library (Architecture ). padCol = 8 padRow = 36 version_id = "00000000000000010000000000000001" Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit . Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance in unit . Set user-defined property "CLKFX_DIVIDE = 1" for instance in unit . Set user-defined property "CLKFX_MULTIPLY = 4" for instance in unit . Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit . Set user-defined property "CLKIN_PERIOD = 25.0000000000000000" for instance in unit . Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit . Set user-defined property "DCM_AUTOCALIBRATION = TRUE" for instance in unit . Set user-defined property "DCM_PERFORMANCE_MODE = MAX_SPEED" for instance in unit . Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit . Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit . Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit . Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit . Set user-defined property "FACTORY_JF = F0F0" for instance in unit . Set user-defined property "PHASE_SHIFT = 0" for instance in unit . Set user-defined property "STARTUP_WAIT = FALSE" for instance in unit . Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit . Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance in unit . Set user-defined property "CLKFX_DIVIDE = 1" for instance in unit . Set user-defined property "CLKFX_MULTIPLY = 3" for instance in unit . Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit . Set user-defined property "CLKIN_PERIOD = 25.0000000000000000" for instance in unit . Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit . Set user-defined property "DCM_AUTOCALIBRATION = TRUE" for instance in unit . Set user-defined property "DCM_PERFORMANCE_MODE = MAX_SPEED" for instance in unit . Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit . Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit . Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit . Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit . Set user-defined property "FACTORY_JF = F0F0" for instance in unit . Set user-defined property "PHASE_SHIFT = 0" for instance in unit . Set user-defined property "STARTUP_WAIT = FALSE" for instance in unit . Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit . Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance in unit . Set user-defined property "CLKFX_DIVIDE = 1" for instance in unit . Set user-defined property "CLKFX_MULTIPLY = 5" for instance in unit . Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit . Set user-defined property "CLKIN_PERIOD = 25.0000000000000000" for instance in unit . Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit . Set user-defined property "DCM_AUTOCALIBRATION = TRUE" for instance in unit . Set user-defined property "DCM_PERFORMANCE_MODE = MAX_SPEED" for instance in unit . Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit . Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit . Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit . Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit . Set user-defined property "FACTORY_JF = F0F0" for instance in unit . Set user-defined property "PHASE_SHIFT = 0" for instance in unit . Set user-defined property "STARTUP_WAIT = FALSE" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). oreg = true use_asy = true use_sfr = false Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). oreg = true Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). width = 32 Entity analyzed. Unit generated. Analyzing generic Entity in library (Architecture ). width = 18 Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/trigger_input_sort.vhd". Unit synthesized. Synthesizing Unit . Related source file is "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/asyncin.vhd". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 6 | | Transitions | 18 | | Inputs | 2 | | Outputs | 6 | | Clock | clk120 (rising_edge) | | Reset | reset_n (negative) | | Reset type | asynchronous | | Reset State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/orx.vhd". Unit synthesized. Synthesizing Unit . Related source file is "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/orx.vhd". Unit synthesized. Synthesizing Unit . Related source file is "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/TLMU_clk.vhd". Unit synthesized. Synthesizing Unit . Related source file is "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/trigger_input_filter.vhd". Unit synthesized. Synthesizing Unit . Related source file is "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/or576.vhd". Unit synthesized. Synthesizing Unit . Related source file is "F:/tk/FH/TRD/pretrigger/TLMU_simple/src/TLMU.vhd". WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:2565 - Inout is never assigned. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:1780 - Signal is never used or assigned. WARNING:Xst:646 - Signal is assigned but never used. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 1152 1-bit register : 1152 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. Optimizing FSM on signal with sequential encoding. ------------------- State | Encoding ------------------- 000 | 000 001 | 001 010 | 010 011 | 011 100 | 101 101 | 100 ------------------- Loading device for application Rf_Device from file '4vlx40.nph' in environment C:\Xilinx91i. ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 2880 Flip-Flops : 2880 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= INFO:Xst:1901 - Instance TLMU_clk_1/DCM_BASE_inst_TA in unit TLMU of type DCM_BASE has been replaced by DCM_ADV INFO:Xst:1901 - Instance TLMU_clk_1/DCM_BASE_inst_120 in unit TLMU of type DCM_BASE has been replaced by DCM_ADV INFO:Xst:1901 - Instance TLMU_clk_1/DCM_BASE_inst_160 in unit TLMU of type DCM_BASE has been replaced by DCM_ADV INFO:Xst:1901 - Instance TLMU_clk_1/BUFGMUX_VIRTEX4_inst in unit TLMU of type BUFGMUX_VIRTEX4 has been replaced by BUFGCTRL Optimizing unit ... Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block TLMU, actual ratio is 10. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 2880 Flip-Flops : 2880 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : ./ise/top.ngr Top Level Output File Name : ./ise/top Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 620 Cell Usage : # BELS : 3465 # BUF : 3 # GND : 1 # LUT2 : 1152 # LUT3 : 4 # LUT4 : 1728 # MUXCY : 576 # VCC : 1 # FlipFlops/Latches : 2880 # FD : 576 # FDC : 1728 # FDR : 576 # Clock Buffers : 5 # BUFG : 4 # BUFGCTRL : 1 # IO Buffers : 610 # IBUF : 577 # IBUFG : 2 # OBUF : 31 # DCM_ADVs : 3 # DCM_ADV : 3 ========================================================================= Device utilization summary: --------------------------- Selected Device : 4vlx40ff1148-11 Number of Slices: 1944 out of 18432 10% Number of Slice Flip Flops: 2880 out of 36864 7% Number of 4 input LUTs: 2884 out of 36864 7% Number of IOs: 620 Number of bonded IOBs: 610 out of 640 95% Number of GCLKs: 5 out of 32 15% Number of DCM_ADVs: 3 out of 8 37% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+--------------------------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+--------------------------------------------+-------+ CLK40_A | BUFGCTRL+TLMU_clk_1/DCM_BASE_inst_120:CLKFX| 2304 | CLK40_A | BUFGCTRL+TLMU_clk_1/DCM_BASE_inst_160:CLK0 | 576 | -----------------------------------+--------------------------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- -----------------------------------+-------------------------------------------------------------------------+-------+ Control Signal | Buffer(FF name) | Load | -----------------------------------+-------------------------------------------------------------------------+-------+ RESET_A_IBUF_3(RESET_A_IBUF_3:O) | NONE(trigger_input_filter_1/multiregs[230].use_asy_g.asyncin_1/cnt_FFd3)| 433 | RESET_A_IBUF_1(RESET_A_IBUF_1:O) | NONE(trigger_input_filter_1/multiregs[511].use_asy_g.asyncin_1/cnt_FFd1)| 433 | RESET_A | IBUF | 429 | RESET_A_IBUF_2(RESET_A_IBUF_2:O) | NONE(trigger_input_filter_1/multiregs[483].use_asy_g.asyncin_1/cnt_FFd3)| 433 | -----------------------------------+-------------------------------------------------------------------------+-------+ Timing Summary: --------------- Speed Grade: -11 Minimum period: 3.432ns (Maximum Frequency: 291.375MHz) Minimum input arrival time before clock: 2.099ns Maximum output required time after clock: 8.219ns Maximum combinational path delay: 8.777ns Timing Detail: -------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'CLK40_A' Clock period: 3.432ns (frequency: 291.375MHz) Total number of paths / destination ports: 6912 / 2304 ------------------------------------------------------------------------- Delay: 1.144ns (Levels of Logic = 1) Source: trigger_input_filter_1/multiregs[575].use_asy_g.asyncin_1/sin (FF) Destination: trigger_input_filter_1/multiregs[575].use_asy_g.asyncin_1/cnt_FFd2 (FF) Source Clock: CLK40_A rising 3.0X Destination Clock: CLK40_A rising 3.0X Data Path: trigger_input_filter_1/multiregs[575].use_asy_g.asyncin_1/sin to trigger_input_filter_1/multiregs[575].use_asy_g.asyncin_1/cnt_FFd2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 2 0.307 0.653 trigger_input_filter_1/multiregs[575].use_asy_g.asyncin_1/sin (trigger_input_filter_1/multiregs[575].use_asy_g.asyncin_1/sin) LUT4:I0->O 1 0.166 0.000 trigger_input_filter_1/multiregs[575].use_asy_g.asyncin_1/cnt_FFd2-In1 (trigger_input_filter_1/multiregs[575].use_asy_g.asyncin_1/cnt_FFd2-In) FDC:D 0.018 trigger_input_filter_1/multiregs[575].use_asy_g.asyncin_1/cnt_FFd2 ---------------------------------------- Total 1.144ns (0.491ns logic, 0.653ns route) (42.9% logic, 57.1% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK40_A' Total number of paths / destination ports: 576 / 576 ------------------------------------------------------------------------- Offset: 2.099ns (Levels of Logic = 1) Source: SA<0> (PAD) Destination: trigger_input_filter_1/multiregs[0].use_asy_g.asyncin_1/sin (FF) Destination Clock: CLK40_A rising 3.0X Data Path: SA<0> to trigger_input_filter_1/multiregs[0].use_asy_g.asyncin_1/sin Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 3 0.867 0.326 SA_0_IBUF (SA_0_IBUF) FDR:R 0.906 trigger_input_filter_1/multiregs[0].use_asy_g.asyncin_1/sin ---------------------------------------- Total 2.099ns (1.773ns logic, 0.326ns route) (84.5% logic, 15.5% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK40_A' Total number of paths / destination ports: 1152 / 2 ------------------------------------------------------------------------- Offset: 8.219ns (Levels of Logic = 51) Source: trigger_input_filter_1/multiregs[371].use_asy_g.asyncin_1/s40 (FF) Destination: T_A<3> (PAD) Source Clock: CLK40_A rising Data Path: trigger_input_filter_1/multiregs[371].use_asy_g.asyncin_1/s40 to T_A<3> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 2 0.307 0.653 trigger_input_filter_1/multiregs[371].use_asy_g.asyncin_1/s40 (trigger_input_filter_1/multiregs[371].use_asy_g.asyncin_1/s40) LUT4:I0->O 1 0.166 0.000 or576_4/orx_2/e_17_or0000_wg_lut<0>2 (N96) MUXCY:S->O 1 0.312 0.000 or576_4/orx_2/e_17_or0000_wg_cy<0>_1 (or576_4/orx_2/e_17_or0000_wg_cy<0>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<1>_1 (or576_4/orx_2/e_17_or0000_wg_cy<1>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<2>_1 (or576_4/orx_2/e_17_or0000_wg_cy<2>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<3>_1 (or576_4/orx_2/e_17_or0000_wg_cy<3>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<4>_1 (or576_4/orx_2/e_17_or0000_wg_cy<4>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<5>_1 (or576_4/orx_2/e_17_or0000_wg_cy<5>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<6>_1 (or576_4/orx_2/e_17_or0000_wg_cy<6>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<7>_1 (or576_4/orx_2/e_17_or0000_wg_cy<7>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<8>_1 (or576_4/orx_2/e_17_or0000_wg_cy<8>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<9>_1 (or576_4/orx_2/e_17_or0000_wg_cy<9>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<10>_1 (or576_4/orx_2/e_17_or0000_wg_cy<10>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<11>_1 (or576_4/orx_2/e_17_or0000_wg_cy<11>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<12>_1 (or576_4/orx_2/e_17_or0000_wg_cy<12>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<13>_1 (or576_4/orx_2/e_17_or0000_wg_cy<13>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<14>_1 (or576_4/orx_2/e_17_or0000_wg_cy<14>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<15>_1 (or576_4/orx_2/e_17_or0000_wg_cy<15>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<16>_1 (or576_4/orx_2/e_17_or0000_wg_cy<16>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<17>_1 (or576_4/orx_2/e_17_or0000_wg_cy<17>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<18>_1 (or576_4/orx_2/e_17_or0000_wg_cy<18>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<19>_1 (or576_4/orx_2/e_17_or0000_wg_cy<19>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<20>_1 (or576_4/orx_2/e_17_or0000_wg_cy<20>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<21>_1 (or576_4/orx_2/e_17_or0000_wg_cy<21>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<22>_1 (or576_4/orx_2/e_17_or0000_wg_cy<22>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<23>_1 (or576_4/orx_2/e_17_or0000_wg_cy<23>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<24>_1 (or576_4/orx_2/e_17_or0000_wg_cy<24>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<25>_1 (or576_4/orx_2/e_17_or0000_wg_cy<25>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<26>_1 (or576_4/orx_2/e_17_or0000_wg_cy<26>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<27>_1 (or576_4/orx_2/e_17_or0000_wg_cy<27>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<28>_1 (or576_4/orx_2/e_17_or0000_wg_cy<28>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<29>_1 (or576_4/orx_2/e_17_or0000_wg_cy<29>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<30>_1 (or576_4/orx_2/e_17_or0000_wg_cy<30>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<31>_1 (or576_4/orx_2/e_17_or0000_wg_cy<31>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<32>_1 (or576_4/orx_2/e_17_or0000_wg_cy<32>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<33>_1 (or576_4/orx_2/e_17_or0000_wg_cy<33>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<34>_1 (or576_4/orx_2/e_17_or0000_wg_cy<34>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<35>_1 (or576_4/orx_2/e_17_or0000_wg_cy<35>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<36>_1 (or576_4/orx_2/e_17_or0000_wg_cy<36>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<37>_1 (or576_4/orx_2/e_17_or0000_wg_cy<37>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<38>_1 (or576_4/orx_2/e_17_or0000_wg_cy<38>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<39>_1 (or576_4/orx_2/e_17_or0000_wg_cy<39>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<40>_1 (or576_4/orx_2/e_17_or0000_wg_cy<40>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<41>_1 (or576_4/orx_2/e_17_or0000_wg_cy<41>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<42>_1 (or576_4/orx_2/e_17_or0000_wg_cy<42>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<43>_1 (or576_4/orx_2/e_17_or0000_wg_cy<43>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<44>_1 (or576_4/orx_2/e_17_or0000_wg_cy<44>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<45>_1 (or576_4/orx_2/e_17_or0000_wg_cy<45>2) MUXCY:CI->O 1 0.038 0.000 or576_4/orx_2/e_17_or0000_wg_cy<46>_1 (or576_4/orx_2/e_17_or0000_wg_cy<46>2) MUXCY:CI->O 1 0.315 0.638 or576_4/orx_2/e_17_or0000_wg_cy<47>_1 (or576_4/orx_2/e_17_or0000_wg_cy<47>2) LUT3:I0->O 1 0.166 0.313 or576_4/orx_2/e_17_or000011 (T_A_3_OBUF) OBUF:I->O 3.601 T_A_3_OBUF (T_A<3>) ---------------------------------------- Total 8.219ns (6.615ns logic, 1.604ns route) (80.5% logic, 19.5% route) ========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 1152 / 2 ------------------------------------------------------------------------- Delay: 8.777ns (Levels of Logic = 52) Source: SB<179> (PAD) Destination: T_A<2> (PAD) Data Path: SB<179> to T_A<2> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 3 0.867 0.651 SB_179_IBUF (SB_179_IBUF) LUT4:I0->O 1 0.166 0.000 or576_3/orx_2/e_17_or0000_wg_lut<0>2 (N240) MUXCY:S->O 1 0.312 0.000 or576_3/orx_2/e_17_or0000_wg_cy<0>_1 (or576_3/orx_2/e_17_or0000_wg_cy<0>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<1>_1 (or576_3/orx_2/e_17_or0000_wg_cy<1>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<2>_1 (or576_3/orx_2/e_17_or0000_wg_cy<2>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<3>_1 (or576_3/orx_2/e_17_or0000_wg_cy<3>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<4>_1 (or576_3/orx_2/e_17_or0000_wg_cy<4>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<5>_1 (or576_3/orx_2/e_17_or0000_wg_cy<5>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<6>_1 (or576_3/orx_2/e_17_or0000_wg_cy<6>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<7>_1 (or576_3/orx_2/e_17_or0000_wg_cy<7>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<8>_1 (or576_3/orx_2/e_17_or0000_wg_cy<8>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<9>_1 (or576_3/orx_2/e_17_or0000_wg_cy<9>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<10>_1 (or576_3/orx_2/e_17_or0000_wg_cy<10>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<11>_1 (or576_3/orx_2/e_17_or0000_wg_cy<11>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<12>_1 (or576_3/orx_2/e_17_or0000_wg_cy<12>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<13>_1 (or576_3/orx_2/e_17_or0000_wg_cy<13>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<14>_1 (or576_3/orx_2/e_17_or0000_wg_cy<14>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<15>_1 (or576_3/orx_2/e_17_or0000_wg_cy<15>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<16>_1 (or576_3/orx_2/e_17_or0000_wg_cy<16>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<17>_1 (or576_3/orx_2/e_17_or0000_wg_cy<17>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<18>_1 (or576_3/orx_2/e_17_or0000_wg_cy<18>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<19>_1 (or576_3/orx_2/e_17_or0000_wg_cy<19>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<20>_1 (or576_3/orx_2/e_17_or0000_wg_cy<20>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<21>_1 (or576_3/orx_2/e_17_or0000_wg_cy<21>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<22>_1 (or576_3/orx_2/e_17_or0000_wg_cy<22>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<23>_1 (or576_3/orx_2/e_17_or0000_wg_cy<23>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<24>_1 (or576_3/orx_2/e_17_or0000_wg_cy<24>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<25>_1 (or576_3/orx_2/e_17_or0000_wg_cy<25>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<26>_1 (or576_3/orx_2/e_17_or0000_wg_cy<26>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<27>_1 (or576_3/orx_2/e_17_or0000_wg_cy<27>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<28>_1 (or576_3/orx_2/e_17_or0000_wg_cy<28>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<29>_1 (or576_3/orx_2/e_17_or0000_wg_cy<29>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<30>_1 (or576_3/orx_2/e_17_or0000_wg_cy<30>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<31>_1 (or576_3/orx_2/e_17_or0000_wg_cy<31>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<32>_1 (or576_3/orx_2/e_17_or0000_wg_cy<32>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<33>_1 (or576_3/orx_2/e_17_or0000_wg_cy<33>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<34>_1 (or576_3/orx_2/e_17_or0000_wg_cy<34>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<35>_1 (or576_3/orx_2/e_17_or0000_wg_cy<35>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<36>_1 (or576_3/orx_2/e_17_or0000_wg_cy<36>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<37>_1 (or576_3/orx_2/e_17_or0000_wg_cy<37>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<38>_1 (or576_3/orx_2/e_17_or0000_wg_cy<38>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<39>_1 (or576_3/orx_2/e_17_or0000_wg_cy<39>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<40>_1 (or576_3/orx_2/e_17_or0000_wg_cy<40>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<41>_1 (or576_3/orx_2/e_17_or0000_wg_cy<41>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<42>_1 (or576_3/orx_2/e_17_or0000_wg_cy<42>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<43>_1 (or576_3/orx_2/e_17_or0000_wg_cy<43>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<44>_1 (or576_3/orx_2/e_17_or0000_wg_cy<44>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<45>_1 (or576_3/orx_2/e_17_or0000_wg_cy<45>2) MUXCY:CI->O 1 0.038 0.000 or576_3/orx_2/e_17_or0000_wg_cy<46>_1 (or576_3/orx_2/e_17_or0000_wg_cy<46>2) MUXCY:CI->O 1 0.315 0.638 or576_3/orx_2/e_17_or0000_wg_cy<47>_1 (or576_3/orx_2/e_17_or0000_wg_cy<47>2) LUT3:I0->O 1 0.166 0.313 or576_3/orx_2/e_17_or000011 (T_A_2_OBUF) OBUF:I->O 3.601 T_A_2_OBUF (T_A<2>) ---------------------------------------- Total 8.777ns (7.175ns logic, 1.602ns route) (81.7% logic, 18.3% route) ========================================================================= CPU : 48.39 / 51.34 s | Elapsed : 49.00 / 52.00 s --> Total memory usage is 305196 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 15 ( 0 filtered) Number of infos : 4 ( 0 filtered)