Release 9.1.03i - par J.33
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Mon Nov 08 19:48:17 2010

All signals are completely routed.

WARNING:ParHelpers:361 - There are 10 loadless signals in this design. This design will cause Bitgen to issue DRC
   warnings.

   EN_A_IBUF
   EN_B_IBUF
   RESET_B_IBUF
   SCSN_IN_A_IBUF
   SCSN_IN_B_IBUF
   SPA_A_IBUF
   SPA_B_IBUF
   SPB_A_IBUF
   SPB_B_IBUF
   T_Data_IBUF