Release 9.1.03i par J.33 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. IBOTS:: Mon Nov 08 19:47:59 2010 par -pl high -w -intstyle xflow ise/top_map.ncd ise/top.ncd ise/top.pcf Constraints file: ise/top.pcf. Loading device for application Rf_Device from file '4vlx40.nph' in environment C:\Xilinx91i. "TLMU" is an NCD, version 3.1, device xc4vlx40, package ff1148, speed -11 This design is using the default stepping level (major silicon revision) for this device (1). Unless your design is targeted at devices of this stepping level, it is recommended that you explicitly specify the stepping level of the parts you will be using. This will allow the tools to take advantage of any available performance and functional enhancements for this device. The latest stepping level for this device is '2'. Additional information on "stepping level" is available at support.xilinx.com. Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) Device speed data version: "PRODUCTION 1.64 2007-03-08". WARNING:Par:251 - Map -timing was run with a lower effort level setting than you are using for PAR. Xilinx recommends that you rerun Map -timing with the effort level that you have set in PAR to achieve better design performance. INFO:Par:253 - The Map -timing placement will be retained since it is likely to achieve better performance. Device Utilization Summary: Number of BUFGs 2 out of 32 6% Number of BUFGCTRLs 1 out of 32 3% Number of DCM_ADVs 2 out of 8 25% Number of External IOBs 620 out of 640 96% Number of LOCed IOBs 620 out of 620 100% Number of Slices 2535 out of 18432 13% Number of SLICEMs 0 out of 9216 0% Overall effort level (-ol): Standard Router effort level (-rl): Standard Starting initial Timing Analysis. REAL time: 8 secs Finished initial Timing Analysis. REAL time: 8 secs WARNING:Par:288 - The signal SCSN_IN_A_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal SCSN_IN_B_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal EN_A_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal EN_B_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal SPA_A_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal SPA_B_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal SPB_A_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal SPB_B_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal T_Data_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal RESET_B_IBUF has no load. PAR will not attempt to route this signal. Starting Router Phase 1: 14221 unrouted; REAL time: 9 secs Phase 2: 11290 unrouted; REAL time: 9 secs Phase 3: 2833 unrouted; REAL time: 11 secs Phase 4: 2833 unrouted; (0) REAL time: 11 secs Phase 5: 2833 unrouted; (0) REAL time: 11 secs Phase 6: 2833 unrouted; (0) REAL time: 11 secs Phase 7: 0 unrouted; (0) REAL time: 13 secs Phase 8: 0 unrouted; (0) REAL time: 14 secs Phase 9: 0 unrouted; (0) REAL time: 15 secs Total REAL time to Router completion: 15 secs Total CPU time to Router completion: 14 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | clk120 | BUFGCTRL_X0Y1| No | 1771 | 0.252 | 2.474 | +---------------------+--------------+------+------+------------+-------------+ | clk40 | BUFGCTRL_X0Y5| No | 502 | 0.236 | 2.400 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. The Delay Summary Report The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for this design is: 1.405 The MAXIMUM PIN DELAY IS: 6.706 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 5.288 Listing Pin Delays by value: (nsec) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 7.00 d >= 7.00 --------- --------- --------- --------- --------- --------- 7841 1071 3130 785 748 0 Timing Score: 0 Number of Timing Constraints that were not applied: 1 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ------------------------------------------------------------------------------------------------------ Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ------------------------------------------------------------------------------------------------------ NET "clk120" PERIOD = 8.333 ns HIGH 50% | SETUP | 6.461ns| 1.872ns| 0| 0 | HOLD | 0.382ns| | 0| 0 ------------------------------------------------------------------------------------------------------ NET "clk40" PERIOD = 25 ns HIGH 50% | N/A | N/A| N/A| N/A| N/A ------------------------------------------------------------------------------------------------------ All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. Generating Pad Report. All signals are completely routed. WARNING:Par:283 - There are 10 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. Total REAL time to PAR completion: 17 secs Total CPU time to PAR completion: 16 secs Peak Memory Usage: 324 MB Placer: Placement generated during map. Routing: Completed - No errors found. Timing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 13 Number of info messages: 1 Writing design to file ise/top.ncd PAR done!