library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity orx is

  generic (
    width : integer := 5);

  port (
    ix : in  std_logic_vector(width-1 downto 0);
    ox : out std_logic);

end orx;

architecture behv of orx is

  signal s : std_logic_vector(width-1  downto 0);
  signal e : std_logic_vector(width-1 downto 0);
  
begin  -- behv

  s    <= ix;
  e(0) <= s(0);

  orgen : for i in 1 to width-1 generate
    e(i) <= e(i-1) or s(i);
  end generate orgen;

  ox <= e(width-1);

end behv;