library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity or576 is
  
  port (
    i : in  std_logic_vector(575 downto 0);
    o : out std_logic);

end or576;

architecture behv of or576 is

  component orx
    generic (
      width : integer);
    port (
      ix : in  std_logic_vector(width-1 downto 0);
      ox : out std_logic);
  end component;

  signal oi : std_logic_vector(17 downto 0);
  signal oii : std_logic;
  
begin  -- behv

  genor32p: for c in 0 to 17 generate


    
    orx_1: orx
      generic map (
        width => 32)
      port map (
        ix => i(32*c+31 downto 32*c),
        ox => oi(c) ) ;
  end generate genor32p;
  

  orx_2: orx
    generic map (
      width => 18)
    port map (
      ix => oi,
      ox => oii);

  o <= oii;
end behv;