library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; -- Coincidence Matrix: -- The 576 pre-filtered inputs are combined in 18x32 ORs to form 18 inputs for -- the coincidence matrix of 18x18 contains 153 entries (18*18-18)/2: -- -- -- -- 16-17 -- 0x211 -- -- 15-16 15-17 -- 0x1f0 0x1f1 -- -- 14-15 14-16 14-17 -- 0x1cf 0x1d0 0x1d1 -- -- 13-14 13-15 13-16 13-17 -- 0x1ae 0x1af 0x1b0 0x1b1 -- -- 12-13 12-14 12-15 12-16 12-17 -- 0x18d 0x18e 0x18f 0x190 0x191 -- -- 11-12 11-13 11-14 11-15 11-16 11-17 -- 0x16c 0x16d 0x16e 0x16f 0x170 0x171 -- -- 10-11 10-12 10-13 10-14 10-15 10-16 10-17 -- 0x14b 0x14c 0x14d 0x14e 0x14f 0x150 0x151 -- -- 09-10 09-11 09-12 09-13 09-14 09-15 09-16 09-17 -- 0x12a 0x12b 0x12c 0x12d 0x12e 0x12f 0x130 0x131 -- -- 08-09 08-10 08-11 08-12 08-13 08-14 08-15 08-16 08-17 -- 0x109 0x10a 0x10b 0x10c 0x10d 0x10e 0x10f 0x110 0x111 -- -- 07-08 07-09 07-10 07-11 07-12 07-13 07-14 07-15 07-16 07-17 -- 0x0e8 0x0e9 0x0ea 0x0eb 0x0ec 0x0ed 0x0ee 0x0ef 0x0f0 0x0f1 -- -- 06-07 06-08 06-09 06-10 06-11 06-12 06-13 06-14 06-15 06-16 06-17 -- 0x0c7 0x0c8 0x0c9 0x0ca 0x0cb 0x0cc 0x0cd 0x0ce 0x0cf 0x0d0 0x0d1 -- -- 05-06 05-07 05-08 05-09 05-10 05-11 05-12 05-13 05-14 05-15 05-16 05-17 -- 0x0a6 0x0a7 0x0a8 0x0a9 0x0aa 0x0ab 0x0ac 0x0ad 0x0ae 0x0af 0x0b0 0x0b1 -- -- 04-05 04-06 04-07 04-08 04-09 04-10 04-11 04-12 04-13 04-14 04-15 04-16 04-17 -- 0x085 0x086 0x087 0x088 0x089 0x08a 0x08b 0x08c 0x08d 0x08e 0x08f 0x090 0x091 -- -- 03-04 03-05 03-06 03-07 03-08 03-09 03-10 03-11 03-12 03-13 03-14 03-15 03-16 03-17 -- 0x064 0x065 0x066 0x067 0x068 0x069 0x06a 0x06b 0x06c 0x06d 0x06e 0x06f 0x070 0x071 -- -- 02-03 02-04 02-05 02-06 02-07 02-08 02-09 02-10 02-11 02-12 02-13 02-14 02-15 02-16 02-17 -- 0x043 0x044 0x045 0x046 0x047 0x048 0x049 0x04a 0x04b 0x04c 0x04d 0x04e 0x04f 0x050 0x051 -- -- 01-02 01-03 01-04 01-05 01-06 01-07 01-08 01-09 01-10 01-11 01-12 01-13 01-14 01-15 01-16 01-17 -- 0x022 0x023 0x024 0x025 0x026 0x027 0x028 0x029 0x02a 0x02b 0x02c 0x02d 0x02e 0x02f 0x030 0x031 -- -- 00-01 00-02 00-03 00-04 00-05 00-06 00-07 00-08 00-09 00-10 00-11 00-12 00-13 00-14 00-15 00-16 00-17 -- 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00a 0x00b 0x00c 0x00d 0x00e 0x00f 0x010 0x011 -- -- Addressing of coincidence of 2 SM "sm1","sm2" : Write a '1' to address -- -- address = min(sm1,sm2)* 0x20 + max(sm1,sm2) -- -- Addressing sm1=sm2 or the top part of the matrix will have no effect entity coinc_matrix is generic( width : integer := 576 ); port ( reset_n : in std_logic; clk : in std_logic; S_in : in std_logic_vector(width-1 downto 0); trigger : out std_logic; we : in std_logic; address : in std_logic_vector(9 downto 0); coinc_matrix_IBO : in std_logic_vector(31 downto 0); coinc_matrix_OBI : out std_logic_vector(31 downto 0)); end coinc_matrix; architecture behv of coinc_matrix is component coinc_line generic ( firstx : integer; lastx : integer; awidth : integer); port ( clk : in std_logic; reset_n : in std_logic; address : in std_logic_vector(awidth-1 downto 0); we : in std_logic; d : in std_logic; dout : out std_logic; yin : in std_logic; xin : in std_logic_vector(17 downto 0); trigger : out std_logic); end component; subtype supermodule_t is std_logic_vector(31 downto 0); type sm_arr_t is array(0 to 17) of supermodule_t; signal sm_arr : sm_arr_t; constant zero_sm : supermodule_t := (others => '0'); constant zero_trigi : std_logic_vector(16 downto 0) := (others => '0'); signal sm : std_logic_vector(17 downto 0); signal trigger_i : std_logic_vector(16 downto 0); signal we_i : std_logic_vector(16 downto 0); signal dout_i : std_logic_vector(31 downto 0); begin -- behv -- Supermodule 0 consists of 16 Bit from A side (0..15) and 16 Bit from -- C-Side: (288..303) or_g : for i in 0 to 17 generate sm_arr(i) <= S_in( ((i*32) + 31) downto (i*32) ); sm(i) <= '1' when sm_arr(i) /= zero_sm else '0'; end generate or_g; we_g : for i in 0 to 16 generate we_i(i) <= '1' when we = '1' and conv_integer(address(9 downto 5)) = i else '0'; end generate we_g; -- lines: first number LL-XX mcell_genx : for lines in 0 to 16 generate coinc_line_m : coinc_line generic map ( firstx => lines+1, lastx => 17, awidth => 5) port map ( clk => clk, reset_n => reset_n, address => address(4 downto 0), we => we_i(lines), d => coinc_matrix_IBO(0), dout => dout_i(lines), yin => sm(lines), xin => sm, trigger => trigger_i(lines)); end generate mcell_genx; coinc_matrix_OBI(0) <= dout_i(conv_integer(address(9 downto 5))); coinc_matrix_OBI(31 downto 1) <= (others => '0'); trigger <= '1' when trigger_i /= zero_trigi else '0'; end behv;