------------------------------------------------------------------------------- -- Address Demultiplexer for SCSN reads ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- 16 address bits (65536 Addresses) -- 2 * 288 channels = 576 = 10 Bits per channel (1024>576) -- Need two addresses for one couner value (48Bit) -- 6 Bits left --> 64 Banks á 1024 channels -- -- Bank 0: (Addr 0x0000 ... 0x03ff): general Info version/temperature/LEDs etc -- Bank 1: (Addr 0x0400 ... 0x07ff): Output switch -- Bank 2: (Addr 0x0800 ... 0x0bff): counter -- Bank 3: (Addr 0x0c00 ... 0x0fff): Trigger stretch/short signals -- Bank 4: (Addr 0x1000 ... 0x13ff): Trigger Input Mask -- Bank 5: (Addr 0x1400 ... 0x17ff): Coincidence Matrix 0 -- Bank 6: (Addr 0x1800 ... 0x1bff): Coincidence Counter 0 -- Bank 7: (Addr 0x1c00 ... 0x1fff): Multiplicity Unit -- Bank 8: (Addr 0x2000 ... 0x23ff): Coincidence Matrix 1 -- Bank 9: (Addr 0x2400 ... 0x27ff): Coincidence Matrix 2 -- Bank 10: (Addr 0x2800 ... 0x2bff): Coincidence Counter 1 -- Bank 11: (Addr 0x2c00 ... 0x2fff): Coincidence Counter 2 -- Bank 12: (Addr 0x3000 ... 0x33ff): Trigger Sequencer, exactly one Bank -- Bank 13: (Addr 0x3400 ... 0x37ff): SOR / EOR Counter -- Bank 14: - -- Bank 15: - -- Bank 16: (Addr 0x4000 ... 0x43ff): Timing analyzer -- ... -- Bank 28: (Addr 0x7000 ... 0x73ff): Timing analyzer control -- Bank 29..31 : (Addr 0x7400 ... 0x7fff): Timing analyzer reserved -- Bank 32: tlmusend -- Bank 33..63: - ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; library work; use work.buildstamp.all; entity adremux is port ( bus_addr : in std_logic_vector(15 downto 0); bus_din : out std_logic_vector(31 downto 0); bus_we : in std_logic; bus_req : in std_logic; id_register_OBI : in std_logic_vector(31 downto 0); led_register_OBI : in std_logic_vector(31 downto 0); AB_OBI : in std_logic_vector(31 downto 0); counter_OBI : in std_logic_vector(31 downto 0); mask_OBI : in std_logic_vector(31 downto 0); coinc_matrix0_OBI : in std_logic_vector(31 downto 0); coinc_matrix1_OBI : in std_logic_vector(31 downto 0); coinc_matrix2_OBI : in std_logic_vector(31 downto 0); ccnt0_OBI : in std_logic_vector(31 downto 0); ccnt1_OBI : in std_logic_vector(31 downto 0); ccnt2_OBI : in std_logic_vector(31 downto 0); TA_OBI : in std_logic_vector(31 downto 0); multi_OBI : in std_logic_vector(31 downto 0); trigger_input_stretch_OBI : in std_logic_vector(31 downto 0); tseq_OBI : in std_logic_vector(31 downto 0); oswitch_OBI : in std_logic_vector(31 downto 0); secnt_OBI : in std_logic_vector(31 downto 0); tsens_OBI : in std_logic_vector(31 downto 0); tlmusend_OBI : in std_logic_vector(31 downto 0); led_register_we : out std_logic; count_we : out std_logic; count_rd : out std_logic; mask_we : out std_logic; coinc_matrix0_we : out std_logic; coinc_matrix1_we : out std_logic; coinc_matrix2_we : out std_logic; ccnt0_we : out std_logic; ccnt1_we : out std_logic; ccnt2_we : out std_logic; TA_we : out std_logic; multi_we : out std_logic; trigger_input_stretch_we : out std_logic; tseq_we : out std_logic; oswitch_we : out std_logic; secnt_we : out std_logic; tsens_we : out std_logic; tlmusend_we : out std_logic); end adremux; architecture behv of adremux is signal bank : std_logic_vector(5 downto 0); signal bankaddr : std_logic_vector(9 downto 0); signal b00d : std_logic_vector(31 downto 0); -- bank 0 data begin -- behv bank <= bus_addr(15 downto 10); bankaddr <= bus_addr(9 downto 0); ----------------------------------------------------------------------------- -- top-level multiplexer ----------------------------------------------------------------------------- tlmux_p : process (bank, b00d, oswitch_OBI, counter_OBI, trigger_input_stretch_OBI, mask_OBI, coinc_matrix0_OBI, ccnt0_OBI, multi_OBI, coinc_matrix1_OBI, coinc_matrix2_OBI, ccnt1_OBI, ccnt2_OBI, tseq_OBI, TA_OBI) begin -- process tlmux_p case bank is when "000000" => bus_din <= b00d; -- Bank 0 individuals when "000001" => bus_din <= oswitch_OBI; -- Bank 1 output switch when "000010" => bus_din <= counter_OBI; -- Bank 2 no sub demux necessary when "000011" => bus_din <= trigger_input_stretch_OBI; -- Bank 3 trigger stretch/short when "000100" => bus_din <= mask_OBI; -- Bank 4 Trigger Input Mask when "000101" => bus_din <= coinc_matrix0_OBI; -- Bank 5 Coincidence Matrix 0 when "000110" => bus_din <= ccnt0_OBI; -- Bank 6 Coincidence Counter 0 when "000111" => bus_din <= multi_OBI; -- Bank 7 Multiplicity Unit/Counter when "001000" => bus_din <= coinc_matrix1_OBI; -- Bank 8 Coincidence Matrix 1 when "001001" => bus_din <= coinc_matrix2_OBI; -- Bank 9 Coincidence Matrix 2 when "001010" => bus_din <= ccnt1_OBI; -- Bank 10 Coincidence Counter 1 when "001011" => bus_din <= ccnt2_OBI; -- Bank 11 Coincidence Counter 2 when "001100" => bus_din <= tseq_OBI; -- Bank 12 Trigger Sequencer when "001101" => bus_din <= secnt_OBI; -- Bank 13 soreor counter when "010000" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "010001" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "010010" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "010011" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "010100" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "010101" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "010110" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "010111" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "011000" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "011001" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "011010" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "011011" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "011100" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "011101" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "011110" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "011111" => bus_din <= TA_OBI; -- Bank 16..31 Timing analyzer when "100000" => bus_din <= tlmusend_OBI; -- Bank 32 tlmusend when others => bus_din <= (others => '0'); end case; end process tlmux_p; -- For autoincrement counter read: count_rd <= '1' when bus_req = '1' and bank(5 downto 0) = "000010" else '0'; -- individual we signals oswitch_we <= '1' when bus_we = '1' and bank(5 downto 0) = "000001" else '0'; count_we <= '1' when bus_we = '1' and bank(5 downto 0) = "000010" else '0'; trigger_input_stretch_we <= '1' when bus_we = '1' and bank(5 downto 0) = "000011" else '0'; mask_we <= '1' when bus_we = '1' and bank(5 downto 0) = "000100" else '0'; coinc_matrix0_we <= '1' when bus_we = '1' and bank(5 downto 0) = "000101" else '0'; TA_we <= '1' when bus_we = '1' and bank(5 downto 4) = "01" else '0'; ccnt0_we <= '1' when bus_we = '1' and bank(5 downto 0) = "000110" else '0'; multi_we <= '1' when bus_we = '1' and bank(5 downto 0) = "000111" else '0'; coinc_matrix1_we <= '1' when bus_we = '1' and bank(5 downto 0) = "001000" else '0'; coinc_matrix2_we <= '1' when bus_we = '1' and bank(5 downto 0) = "001001" else '0'; ccnt1_we <= '1' when bus_we = '1' and bank(5 downto 0) = "001010" else '0'; ccnt2_we <= '1' when bus_we = '1' and bank(5 downto 0) = "001011" else '0'; tseq_we <= '1' when bus_we = '1' and bank(5 downto 0) = "001100" else '0'; secnt_we <= '1' when bus_we = '1' and bank(5 downto 0) = "001101" else '0'; tlmusend_we <= '1' when bus_we = '1' and bank(5 downto 0) = "100000" else '0'; ----------------------------------------------------------------------------- -- Bank 0 Mux ----------------------------------------------------------------------------- b00d_p : process (bankaddr, id_register_OBI, led_register_OBI) begin -- process b00d_p case bankaddr is when "0000000000" => b00d <= (31 downto 16 => '0') & build_rev; when "0000000001" => b00d <= build_date; when "0000000010" => b00d <= (31 downto 1 => '0') & build_modified; when "0000000011" => b00d <= id_register_OBI; when "0000000100" => b00d <= led_register_OBI; when "0000000101" => b00d <= AB_OBI; -- addr 8 for Temperature sensor control (9..F reserved (for tsens_we, -- s. below)) when "0000001000" => b00d <= tsens_OBI; -- when "0000001001" => b00d <= tsens_OBI; -- ... -- when "0000001111" => b00d <= tsens_OBI; when others => b00d <= (others => '0'); end case; end process b00d_p; led_register_we <= '1' when bus_we = '1' and bus_addr = x"0004" else '0'; tsens_we <= '1' when bus_we = '1' and bus_addr(15 downto 3) = "0000000000001" else '0'; end behv;